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[PULL 17/40] target/riscv: Add AIA cpu feature
From: |
Alistair Francis |
Subject: |
[PULL 17/40] target/riscv: Add AIA cpu feature |
Date: |
Sat, 12 Feb 2022 10:00:08 +1000 |
From: Anup Patel <anup.patel@wdc.com>
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 283a3cda4b..8838c61ae4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -78,7 +78,8 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
- RISCV_FEATURE_MISA
+ RISCV_FEATURE_MISA,
+ RISCV_FEATURE_AIA
};
#define PRIV_VERSION_1_10_0 0x00011000
--
2.34.1
- [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext, (continued)
- [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/11
- [PULL 08/40] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/11
- [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/11
- [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/11
- [PULL 11/40] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/11
- [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/11
- [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/11
- [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/11
- [PULL 15/40] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2022/02/11
- [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation, Alistair Francis, 2022/02/11
- [PULL 17/40] target/riscv: Add AIA cpu feature,
Alistair Francis <=
- [PULL 18/40] target/riscv: Add defines for AIA CSRs, Alistair Francis, 2022/02/11
- [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 2022/02/11
- [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 2022/02/11
- [PULL 20/40] target/riscv: Implement AIA local interrupt priorities, Alistair Francis, 2022/02/11
- [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs, Alistair Francis, 2022/02/11
- [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available, Alistair Francis, 2022/02/11
- [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/11
- [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/11
- [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/11
- [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/11