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[PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs
From: |
Alistair Francis |
Subject: |
[PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs |
Date: |
Sat, 12 Feb 2022 10:00:14 +1000 |
From: Anup Patel <anup.patel@wdc.com>
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-13-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 46448a2b7e..89700038fb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -158,6 +158,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
}
+static int aia_any(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return any(env, csrno);
+}
+
static int aia_any32(CPURISCVState *env, int csrno)
{
if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -568,6 +577,12 @@ static RISCVException read_zero(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException write_ignore(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -2598,9 +2613,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
+ /* Virtual Interrupts for Supervisor Level (AIA) */
+ [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
+ [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
+
/* Machine-Level High-Half CSRs (AIA) */
[CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
[CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
+ [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore },
+ [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore },
[CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
/* Supervisor Trap Setup */
@@ -2654,12 +2675,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { "mtinst", hmode, read_mtinst,
write_mtinst },
/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl
},
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1,
write_hviprio1 },
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2,
write_hviprio2 },
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh
},
+ [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore
},
[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
write_hviprio1h },
[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
write_hviprio2h },
--
2.34.1
- [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation, (continued)
- [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation, Alistair Francis, 2022/02/11
- [PULL 17/40] target/riscv: Add AIA cpu feature, Alistair Francis, 2022/02/11
- [PULL 18/40] target/riscv: Add defines for AIA CSRs, Alistair Francis, 2022/02/11
- [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 2022/02/11
- [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 2022/02/11
- [PULL 20/40] target/riscv: Implement AIA local interrupt priorities, Alistair Francis, 2022/02/11
- [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs, Alistair Francis, 2022/02/11
- [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available, Alistair Francis, 2022/02/11
- [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/11
- [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/11
- [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs,
Alistair Francis <=
- [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/11
- [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/11
- [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/11
- [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/02/11
- [PULL 33/40] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/02/11
- [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs, Alistair Francis, 2022/02/11
- [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/11
- [PULL 37/40] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/11