[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg i
From: |
Alistair Francis |
Subject: |
[PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' |
Date: |
Wed, 16 Feb 2022 16:28:41 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 78 ++++++++++++++++++++++++----------------------
1 file changed, 41 insertions(+), 37 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 55635d68d5..1175915c0d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -303,6 +303,46 @@ struct RISCVCPUClass {
DeviceReset parent_reset;
};
+struct RISCVCPUConfig {
+ bool ext_i;
+ bool ext_e;
+ bool ext_g;
+ bool ext_m;
+ bool ext_a;
+ bool ext_f;
+ bool ext_d;
+ bool ext_c;
+ bool ext_s;
+ bool ext_u;
+ bool ext_h;
+ bool ext_j;
+ bool ext_v;
+ bool ext_zba;
+ bool ext_zbb;
+ bool ext_zbc;
+ bool ext_zbs;
+ bool ext_counters;
+ bool ext_ifencei;
+ bool ext_icsr;
+ bool ext_zfh;
+ bool ext_zfhmin;
+ bool ext_zve32f;
+ bool ext_zve64f;
+
+ char *priv_spec;
+ char *user_spec;
+ char *bext_spec;
+ char *vext_spec;
+ uint16_t vlen;
+ uint16_t elen;
+ bool mmu;
+ bool pmp;
+ bool epmp;
+ uint64_t resetvec;
+};
+
+typedef struct RISCVCPUConfig RISCVCPUConfig;
+
/**
* RISCVCPU:
* @env: #CPURISCVState
@@ -320,43 +360,7 @@ struct RISCVCPU {
char *dyn_vreg_xml;
/* Configuration Settings */
- struct {
- bool ext_i;
- bool ext_e;
- bool ext_g;
- bool ext_m;
- bool ext_a;
- bool ext_f;
- bool ext_d;
- bool ext_c;
- bool ext_s;
- bool ext_u;
- bool ext_h;
- bool ext_j;
- bool ext_v;
- bool ext_zba;
- bool ext_zbb;
- bool ext_zbc;
- bool ext_zbs;
- bool ext_counters;
- bool ext_ifencei;
- bool ext_icsr;
- bool ext_zfh;
- bool ext_zfhmin;
- bool ext_zve32f;
- bool ext_zve64f;
-
- char *priv_spec;
- char *user_spec;
- char *bext_spec;
- char *vext_spec;
- uint16_t vlen;
- uint16_t elen;
- bool mmu;
- bool pmp;
- bool epmp;
- uint64_t resetvec;
- } cfg;
+ RISCVCPUConfig cfg;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
--
2.34.1
- [PULL v2 00/35] riscv-to-apply queue, Alistair Francis, 2022/02/16
- [PULL v2 01/35] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/16
- [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader, Alistair Francis, 2022/02/16
- [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig',
Alistair Francis <=
- [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Alistair Francis, 2022/02/16
- [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/16
- [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/16
- [PULL v2 07/35] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/16
- [PULL v2 08/35] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/16
- [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/16
- [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/16
- [PULL v2 11/35] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/16