[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 07/35] target/riscv: access cfg structure through DisasContext
|
From: |
Alistair Francis |
|
Subject: |
[PULL v2 07/35] target/riscv: access cfg structure through DisasContext |
|
Date: |
Wed, 16 Feb 2022 16:28:44 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 810431a1d6..f9bd3b7ec4 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -19,25 +19,25 @@
*/
#define REQUIRE_ZBA(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
+ if (ctx->cfg_ptr->ext_zba) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBB(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \
+ if (ctx->cfg_ptr->ext_zbb) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBC(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
+ if (ctx->cfg_ptr->ext_zbc) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBS(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
+ if (ctx->cfg_ptr->ext_zbs) { \
return false; \
} \
} while (0)
--
2.34.1
- [PULL v2 00/35] riscv-to-apply queue, Alistair Francis, 2022/02/16
- [PULL v2 01/35] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/16
- [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader, Alistair Francis, 2022/02/16
- [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Alistair Francis, 2022/02/16
- [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Alistair Francis, 2022/02/16
- [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/16
- [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/16
- [PULL v2 07/35] target/riscv: access cfg structure through DisasContext,
Alistair Francis <=
- [PULL v2 08/35] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/16
- [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/16
- [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/16
- [PULL v2 11/35] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/16
- [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/16
- [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/16
- [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/16
- [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2022/02/16