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[PULL v2 08/35] target/riscv: iterate over a table of decoders
From: |
Alistair Francis |
Subject: |
[PULL v2 08/35] target/riscv: iterate over a table of decoders |
Date: |
Wed, 16 Feb 2022 16:28:45 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
This commit only adds the new structure and the table, allowing for
the easy addition of additional decoders in the future.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-6-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 32 +++++++++++++++++++++++++++-----
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f19d5cd0c0..30b1b68341 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -111,6 +111,11 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa_ext & ext;
}
+static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
+{
+ return true;
+}
+
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
@@ -855,15 +860,26 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
target_ulong pc)
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
- /* check for compressed insn */
+ /*
+ * A table with predicate (i.e., guard) functions and decoder functions
+ * that are tested in-order until a decoder matches onto the opcode.
+ */
+ static const struct {
+ bool (*guard_func)(DisasContext *);
+ bool (*decode_func)(DisasContext *, uint32_t);
+ } decoders[] = {
+ { always_true_p, decode_insn32 },
+ };
+
+ /* Check for compressed insn */
if (extract16(opcode, 0, 2) != 3) {
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- if (!decode_insn16(ctx, opcode)) {
- gen_exception_illegal(ctx);
+ if (decode_insn16(ctx, opcode)) {
+ return;
}
}
} else {
@@ -873,10 +889,16 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- if (!decode_insn32(ctx, opcode32)) {
- gen_exception_illegal(ctx);
+
+ for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
+ if (decoders[i].guard_func(ctx) &&
+ decoders[i].decode_func(ctx, opcode32)) {
+ return;
+ }
}
}
+
+ gen_exception_illegal(ctx);
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--
2.34.1
- [PULL v2 00/35] riscv-to-apply queue, Alistair Francis, 2022/02/16
- [PULL v2 01/35] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/16
- [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader, Alistair Francis, 2022/02/16
- [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Alistair Francis, 2022/02/16
- [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Alistair Francis, 2022/02/16
- [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/16
- [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/16
- [PULL v2 07/35] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/16
- [PULL v2 08/35] target/riscv: iterate over a table of decoders,
Alistair Francis <=
- [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/16
- [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/16
- [PULL v2 11/35] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/16
- [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/16
- [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/16
- [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/16
- [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2022/02/16
- [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation, Alistair Francis, 2022/02/16
- [PULL v2 17/35] target/riscv: Add AIA cpu feature, Alistair Francis, 2022/02/16
- [PULL v2 18/35] target/riscv: Add defines for AIA CSRs, Alistair Francis, 2022/02/16