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[PULL 41/87] target/ppc: Implement xxgenpcv[bhwd]m instruction
From: |
Cédric Le Goater |
Subject: |
[PULL 41/87] target/ppc: Implement xxgenpcv[bhwd]m instruction |
Date: |
Wed, 2 Mar 2022 12:07:17 +0100 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-36-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 16 +++++
target/ppc/insn32.decode | 10 ++++
target/ppc/int_helper.c | 91 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 43 ++++++++++++++
4 files changed, 160 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 13034bca58c7..008cd6405d0f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -494,6 +494,22 @@ DEF_HELPER_3(xvrspic, void, env, vsr, vsr)
DEF_HELPER_3(xvrspim, void, env, vsr, vsr)
DEF_HELPER_3(xvrspip, void, env, vsr, vsr)
DEF_HELPER_3(xvrspiz, void, env, vsr, vsr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXPERMX, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, tl)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b8dbac553e33..22b245607b0f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -119,6 +119,9 @@
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
%x_xt 0:1 21:5
+&X_imm5 xt imm:uint8_t vrb
+@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5
xt=%x_xt
+
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8
xt=%x_xt
@@ -615,6 +618,13 @@ XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ...
@XX3_dm
XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
+## VSX Vector Generate PCV
+
+XXGENPCVBM 111100 ..... ..... ..... 1110010100 . @X_imm5
+XXGENPCVHM 111100 ..... ..... ..... 1110010101 . @X_imm5
+XXGENPCVWM 111100 ..... ..... ..... 1110110100 . @X_imm5
+XXGENPCVDM 111100 ..... ..... ..... 1110110101 . @X_imm5
+
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ca59cd3d79ec..b2b17bb1ca5e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1072,6 +1072,97 @@ void helper_VPERMR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t
*b, ppc_avr_t *c)
*r = result;
}
+#define XXGENPCV(NAME, SZ) \
+void glue(helper_, glue(NAME, _be_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
+{ \
+ ppc_vsr_t tmp; \
+ \
+ /* Initialize tmp with the result of an all-zeros mask */ \
+ tmp.VsrD(0) = 0x1011121314151617; \
+ tmp.VsrD(1) = 0x18191A1B1C1D1E1F; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(i) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0; k < SZ; k++) { \
+ tmp.VsrB(i + k) = j + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+} \
+ \
+void glue(helper_, glue(NAME, _be_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
+{ \
+ ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(i) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0; k < SZ; k++) { \
+ tmp.VsrB(j + k) = i + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+} \
+ \
+void glue(helper_, glue(NAME, _le_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
+{ \
+ ppc_vsr_t tmp; \
+ \
+ /* Initialize tmp with the result of an all-zeros mask */ \
+ tmp.VsrD(0) = 0x1F1E1D1C1B1A1918; \
+ tmp.VsrD(1) = 0x1716151413121110; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ /* Reverse indexing of "i" */ \
+ const int idx = ARRAY_SIZE(b->u8) - i - SZ; \
+ if (b->VsrB(idx) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
+ tmp.VsrB(idx + rk) = j + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+} \
+ \
+void glue(helper_, glue(NAME, _le_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
+{ \
+ ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(ARRAY_SIZE(b->u8) - i - SZ) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
+ /* Reverse indexing of "j" */ \
+ const int idx = ARRAY_SIZE(b->u8) - j - SZ; \
+ tmp.VsrB(idx + rk) = i + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+}
+
+XXGENPCV(XXGENPCVBM, 1)
+XXGENPCV(XXGENPCVHM, 2)
+XXGENPCV(XXGENPCVWM, 4)
+XXGENPCV(XXGENPCVDM, 8)
+#undef XXGENPCV
+
#if defined(HOST_WORDS_BIGENDIAN)
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
#define VBPERMD_INDEX(i) (i)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index b5e07cf3df32..6528e1ae31e0 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1256,6 +1256,49 @@ static bool trans_XXPERMX(DisasContext *ctx,
arg_8RR_XX4_uim3 *a)
return true;
}
+#define XXGENPCV(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \
+{ \
+ TCGv_ptr xt, vrb; \
+ \
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310); \
+ REQUIRE_VSX(ctx); \
+ \
+ if (a->imm & ~0x3) { \
+ gen_invalid(ctx); \
+ return true; \
+ } \
+ \
+ xt = gen_vsr_ptr(a->xt); \
+ vrb = gen_avr_ptr(a->vrb); \
+ \
+ switch (a->imm) { \
+ case 0b00000: /* Big-Endian expansion */ \
+ glue(gen_helper_, glue(NAME, _be_exp))(xt, vrb); \
+ break; \
+ case 0b00001: /* Big-Endian compression */ \
+ glue(gen_helper_, glue(NAME, _be_comp))(xt, vrb); \
+ break; \
+ case 0b00010: /* Little-Endian expansion */ \
+ glue(gen_helper_, glue(NAME, _le_exp))(xt, vrb); \
+ break; \
+ case 0b00011: /* Little-Endian compression */ \
+ glue(gen_helper_, glue(NAME, _le_comp))(xt, vrb); \
+ break; \
+ } \
+ \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(vrb); \
+ \
+ return true; \
+}
+
+XXGENPCV(XXGENPCVBM)
+XXGENPCV(XXGENPCVHM)
+XXGENPCV(XXGENPCVWM)
+XXGENPCV(XXGENPCVDM)
+#undef XXGENPCV
+
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.34.1
- [PULL 30/87] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree, (continued)
- [PULL 30/87] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 37/87] target/ppc: Move xxpermdi to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 47/87] target/ppc: Implement xscmp{eq,ge,gt}qp, Cédric Le Goater, 2022/03/02
- [PULL 25/87] target/ppc: move vs[lr][a][bhwd] to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 36/87] target/ppc: move xxperm/xxpermr to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 44/87] target/ppc: Implement xvtlsbb instruction, Cédric Le Goater, 2022/03/02
- [PULL 38/87] target/ppc: Implement xxpermx instruction, Cédric Le Goater, 2022/03/02
- [PULL 52/87] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions, Cédric Le Goater, 2022/03/02
- [PULL 57/87] ppc/xive2: Introduce a presenter matching routine, Cédric Le Goater, 2022/03/02
- [PULL 58/87] ppc/pnv: Add a XIVE2 controller to the POWER10 chip, Cédric Le Goater, 2022/03/02
- [PULL 41/87] target/ppc: Implement xxgenpcv[bhwd]m instruction,
Cédric Le Goater <=
- [PULL 65/87] ppc/xive: Add support for PQ state bits offload, Cédric Le Goater, 2022/03/02
- [PULL 79/87] hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc(), Cédric Le Goater, 2022/03/02
- [PULL 80/87] hw/ppc/spapr_drc.c: use g_autofree in drc_realize(), Cédric Le Goater, 2022/03/02
- [PULL 53/87] target/ppc: implement plxsd/pstxsd, Cédric Le Goater, 2022/03/02
- [PULL 62/87] ppc/pnv: Add a HOMER model to POWER10, Cédric Le Goater, 2022/03/02
- [PULL 40/87] target/ppc: Implement xxeval, Cédric Le Goater, 2022/03/02
- [PULL 49/87] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3, Cédric Le Goater, 2022/03/02
- [PULL 56/87] ppc/xive2: Introduce a XIVE2 core framework, Cédric Le Goater, 2022/03/02
- [PULL 50/87] target/ppc: Refactor VSX_MAX_MINC helper, Cédric Le Goater, 2022/03/02
- [PULL 68/87] pnv/xive2: Introduce new capability bits, Cédric Le Goater, 2022/03/02