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[PULL 25/87] target/ppc: move vs[lr][a][bhwd] to decodetree
From: |
Cédric Le Goater |
Subject: |
[PULL 25/87] target/ppc: move vs[lr][a][bhwd] to decodetree |
Date: |
Wed, 2 Mar 2022 12:07:01 +0100 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-20-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 17 ++++++++++++
target/ppc/translate/vmx-impl.c.inc | 41 +++++++++++++++++++----------
target/ppc/translate/vmx-ops.c.inc | 13 +--------
3 files changed, 45 insertions(+), 26 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 02df4a98e665..88baebe35e4c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -467,6 +467,23 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
+## Vector Integer Shift Instruction
+
+VSLB 000100 ..... ..... ..... 00100000100 @VX
+VSLH 000100 ..... ..... ..... 00101000100 @VX
+VSLW 000100 ..... ..... ..... 00110000100 @VX
+VSLD 000100 ..... ..... ..... 10111000100 @VX
+
+VSRB 000100 ..... ..... ..... 01000000100 @VX
+VSRH 000100 ..... ..... ..... 01001000100 @VX
+VSRW 000100 ..... ..... ..... 01010000100 @VX
+VSRD 000100 ..... ..... ..... 11011000100 @VX
+
+VSRAB 000100 ..... ..... ..... 01100000100 @VX
+VSRAH 000100 ..... ..... ..... 01101000100 @VX
+VSRAW 000100 ..... ..... ..... 01110000100 @VX
+VSRAD 000100 ..... ..... ..... 01111000100 @VX
+
## Vector Integer Arithmetic Instructions
VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 52774cdd4dfb..1b05b0b3a35e 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -799,21 +799,7 @@ static void trans_vclzd(DisasContext *ctx)
}
GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
-GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
-GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
-GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
GEN_VXFORM(vrlwnm, 2, 6);
-GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
- vrlwnm, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);
-GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);
-GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);
-GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);
-GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);
-GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);
-GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);
-GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);
-GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);
GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
@@ -821,6 +807,33 @@ GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
+static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
+ void (*gen_gvec)(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t))
+{
+ REQUIRE_VECTOR(ctx);
+
+ gen_gvec(vece, avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16);
+
+ return true;
+}
+
+TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv);
+TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv);
+TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv);
+TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
+
+TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv);
+TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv);
+TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv);
+TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
+
+TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv);
+TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
+TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
+TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
diff --git a/target/ppc/translate/vmx-ops.c.inc
b/target/ppc/translate/vmx-ops.c.inc
index cb4c5bb953c1..878bce92c6a4 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -102,18 +102,7 @@ GEN_VXFORM_300(vextubrx, 6, 28),
GEN_VXFORM_300(vextuhrx, 6, 29),
GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vmuluwm, 4, 2),
-GEN_VXFORM(vslb, 2, 4),
-GEN_VXFORM(vslh, 2, 5),
-GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_207(vsld, 2, 23),
-GEN_VXFORM(vsrb, 2, 8),
-GEN_VXFORM(vsrh, 2, 9),
-GEN_VXFORM(vsrw, 2, 10),
-GEN_VXFORM_207(vsrd, 2, 27),
-GEN_VXFORM(vsrab, 2, 12),
-GEN_VXFORM(vsrah, 2, 13),
-GEN_VXFORM(vsraw, 2, 14),
-GEN_VXFORM_207(vsrad, 2, 15),
+GEN_VXFORM_300(vrlwnm, 2, 6),
GEN_VXFORM_300(vsrv, 2, 28),
GEN_VXFORM_300(vslv, 2, 29),
GEN_VXFORM(vslo, 6, 16),
--
2.34.1
- [PULL 28/87] target/ppc: implement vsraq, (continued)
- [PULL 28/87] target/ppc: implement vsraq, Cédric Le Goater, 2022/03/02
- [PULL 09/87] target/ppc: Moved vector multiply high and low to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 31/87] target/ppc: implement vrlq, Cédric Le Goater, 2022/03/02
- [PULL 32/87] target/ppc: implement vrlqnm, Cédric Le Goater, 2022/03/02
- [PULL 24/87] target/ppc: implement vgnb, Cédric Le Goater, 2022/03/02
- [PULL 26/87] target/ppc: implement vslq, Cédric Le Goater, 2022/03/02
- [PULL 29/87] target/ppc: move vrl[bhwd] to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 30/87] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 37/87] target/ppc: Move xxpermdi to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 47/87] target/ppc: Implement xscmp{eq,ge,gt}qp, Cédric Le Goater, 2022/03/02
- [PULL 25/87] target/ppc: move vs[lr][a][bhwd] to decodetree,
Cédric Le Goater <=
- [PULL 36/87] target/ppc: move xxperm/xxpermr to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 44/87] target/ppc: Implement xvtlsbb instruction, Cédric Le Goater, 2022/03/02
- [PULL 38/87] target/ppc: Implement xxpermx instruction, Cédric Le Goater, 2022/03/02
- [PULL 52/87] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions, Cédric Le Goater, 2022/03/02
- [PULL 57/87] ppc/xive2: Introduce a presenter matching routine, Cédric Le Goater, 2022/03/02
- [PULL 58/87] ppc/pnv: Add a XIVE2 controller to the POWER10 chip, Cédric Le Goater, 2022/03/02
- [PULL 41/87] target/ppc: Implement xxgenpcv[bhwd]m instruction, Cédric Le Goater, 2022/03/02
- [PULL 65/87] ppc/xive: Add support for PQ state bits offload, Cédric Le Goater, 2022/03/02
- [PULL 79/87] hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc(), Cédric Le Goater, 2022/03/02
- [PULL 80/87] hw/ppc/spapr_drc.c: use g_autofree in drc_realize(), Cédric Le Goater, 2022/03/02