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[PULL 07/13] hw: riscv: opentitan: fixup SPI addresses
From: |
Alistair Francis |
Subject: |
[PULL 07/13] hw: riscv: opentitan: fixup SPI addresses |
Date: |
Thu, 3 Mar 2022 15:27:58 +1000 |
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.
The address references can be found [1].
[1]
https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 4 +++-
hw/riscv/opentitan.c | 12 +++++++++---
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index eac35ef590..00da9ded43 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -57,8 +57,10 @@ enum {
IBEX_DEV_FLASH,
IBEX_DEV_FLASH_VIRTUAL,
IBEX_DEV_UART,
+ IBEX_DEV_SPI_DEVICE,
+ IBEX_DEV_SPI_HOST0,
+ IBEX_DEV_SPI_HOST1,
IBEX_DEV_GPIO,
- IBEX_DEV_SPI,
IBEX_DEV_I2C,
IBEX_DEV_PATTGEN,
IBEX_DEV_TIMER,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index aec7cfa33f..833624d66c 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
[IBEX_DEV_UART] = { 0x40000000, 0x1000 },
[IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
- [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
+ [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 },
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
[IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
[IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
+ [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
+ [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
@@ -209,8 +211,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
- create_unimplemented_device("riscv.lowrisc.ibex.spi",
- memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
+ memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.spi_host0",
+ memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.spi_host1",
+ memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size);
create_unimplemented_device("riscv.lowrisc.ibex.i2c",
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
--
2.35.1
- [PULL 00/13] riscv-to-apply queue, Alistair Francis, 2022/03/03
- [PULL 01/13] target/riscv: fix inverted checks for ext_zb[abcs], Alistair Francis, 2022/03/03
- [PULL 02/13] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Alistair Francis, 2022/03/03
- [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/03/03
- [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/03/03
- [PULL 05/13] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/03/03
- [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs, Alistair Francis, 2022/03/03
- [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses,
Alistair Francis <=
- [PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}, Alistair Francis, 2022/03/03
- [PULL 09/13] target/riscv: hardwire mstatus.FS to zero when enable zfinx, Alistair Francis, 2022/03/03
- [PULL 10/13] target/riscv: add support for zfinx, Alistair Francis, 2022/03/03
- [PULL 11/13] target/riscv: add support for zdinx, Alistair Francis, 2022/03/03
- [PULL 12/13] target/riscv: add support for zhinx/zhinxmin, Alistair Francis, 2022/03/03
- [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties, Alistair Francis, 2022/03/03
- Re: [PULL 00/13] riscv-to-apply queue, Peter Maydell, 2022/03/04