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[PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties
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From: |
Alistair Francis |
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Subject: |
[PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties |
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Date: |
Thu, 3 Mar 2022 15:28:04 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 55371b1aa5..ddda4906ff 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -795,6 +795,11 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
+ DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
+ DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
--
2.35.1
- [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation, (continued)
- [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/03/03
- [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/03/03
- [PULL 05/13] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/03/03
- [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs, Alistair Francis, 2022/03/03
- [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses, Alistair Francis, 2022/03/03
- [PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}, Alistair Francis, 2022/03/03
- [PULL 09/13] target/riscv: hardwire mstatus.FS to zero when enable zfinx, Alistair Francis, 2022/03/03
- [PULL 10/13] target/riscv: add support for zfinx, Alistair Francis, 2022/03/03
- [PULL 11/13] target/riscv: add support for zdinx, Alistair Francis, 2022/03/03
- [PULL 12/13] target/riscv: add support for zhinx/zhinxmin, Alistair Francis, 2022/03/03
- [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties,
Alistair Francis <=
- Re: [PULL 00/13] riscv-to-apply queue, Peter Maydell, 2022/03/04