[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx
From: |
Alistair Francis |
Subject: |
[PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} |
Date: |
Thu, 3 Mar 2022 15:27:59 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu.c | 12 ++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8183fb86d5..9ba05042ed 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -362,8 +362,12 @@ struct RISCVCPUConfig {
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
+ bool ext_zdinx;
bool ext_zfh;
bool ext_zfhmin;
+ bool ext_zfinx;
+ bool ext_zhinx;
+ bool ext_zhinxmin;
bool ext_zve32f;
bool ext_zve64f;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b0a40b83e7..55371b1aa5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -587,6 +587,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
cpu->cfg.ext_d = true;
}
+ if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+ cpu->cfg.ext_zhinxmin) {
+ cpu->cfg.ext_zfinx = true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
@@ -665,6 +670,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_j) {
ext |= RVJ;
}
+ if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
+ cpu->cfg.ext_zfhmin)) {
+ error_setg(errp,
+ "'Zfinx' cannot be supported together with 'F', 'D',
'Zfh',"
+ " 'Zfhmin'");
+ return;
+ }
set_misa(env, env->misa_mxl, ext);
}
--
2.35.1
- [PULL 00/13] riscv-to-apply queue, Alistair Francis, 2022/03/03
- [PULL 01/13] target/riscv: fix inverted checks for ext_zb[abcs], Alistair Francis, 2022/03/03
- [PULL 02/13] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Alistair Francis, 2022/03/03
- [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/03/03
- [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/03/03
- [PULL 05/13] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/03/03
- [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs, Alistair Francis, 2022/03/03
- [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses, Alistair Francis, 2022/03/03
- [PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min},
Alistair Francis <=
- [PULL 09/13] target/riscv: hardwire mstatus.FS to zero when enable zfinx, Alistair Francis, 2022/03/03
- [PULL 10/13] target/riscv: add support for zfinx, Alistair Francis, 2022/03/03
- [PULL 11/13] target/riscv: add support for zdinx, Alistair Francis, 2022/03/03
- [PULL 12/13] target/riscv: add support for zhinx/zhinxmin, Alistair Francis, 2022/03/03
- [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties, Alistair Francis, 2022/03/03
- Re: [PULL 00/13] riscv-to-apply queue, Peter Maydell, 2022/03/04