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[PULL 09/30] tcg/i386: Implement avx512 variable shifts
From: |
Richard Henderson |
Subject: |
[PULL 09/30] tcg/i386: Implement avx512 variable shifts |
Date: |
Thu, 3 Mar 2022 10:59:23 -1000 |
AVX512VL has VPSRAVQ, and
AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 6a53f378cc..055db88422 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -419,9 +419,13 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
+#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
+#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
#define OPC_VZEROUPPER (0x77 | P_EXT)
@@ -2835,16 +2839,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
};
static int const shlv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16. */
- OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ
+ OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
};
static int const shrv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16. */
- OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ
+ OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ
};
static int const sarv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16, MO_64. */
- OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
+ OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ
};
static int const shls_insn[4] = {
OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ
@@ -3335,9 +3336,24 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
- return have_avx2 && vece >= MO_32;
+ switch (vece) {
+ case MO_16:
+ return have_avx512bw;
+ case MO_32:
+ case MO_64:
+ return have_avx2;
+ }
+ return 0;
case INDEX_op_sarv_vec:
- return have_avx2 && vece == MO_32;
+ switch (vece) {
+ case MO_16:
+ return have_avx512bw;
+ case MO_32:
+ return have_avx2;
+ case MO_64:
+ return have_avx512vl;
+ }
+ return 0;
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
return have_avx2 && vece >= MO_32 ? -1 : 0;
--
2.25.1
- [PULL 00/30] tcg patch queue, Richard Henderson, 2022/03/03
- [PULL 01/30] tcg/optimize: only read val after const check, Richard Henderson, 2022/03/03
- [PULL 02/30] tcg: Set MAX_OPC_PARAM_IARGS to 7, Richard Henderson, 2022/03/03
- [PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv, Richard Henderson, 2022/03/03
- [PULL 04/30] tcg/ppc: Implement vector NAND, NOR, EQV, Richard Henderson, 2022/03/03
- [PULL 05/30] tcg/s390x: Implement vector NAND, NOR, EQV, Richard Henderson, 2022/03/03
- [PULL 07/30] tcg/i386: Add tcg_out_evex_opc, Richard Henderson, 2022/03/03
- [PULL 06/30] tcg/i386: Detect AVX512, Richard Henderson, 2022/03/03
- [PULL 08/30] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv, Richard Henderson, 2022/03/03
- [PULL 09/30] tcg/i386: Implement avx512 variable shifts,
Richard Henderson <=
- [PULL 10/30] tcg/i386: Implement avx512 scalar shift, Richard Henderson, 2022/03/03
- [PULL 11/30] tcg/i386: Implement avx512 immediate sari shift, Richard Henderson, 2022/03/03
- [PULL 12/30] tcg/i386: Implement avx512 immediate rotate, Richard Henderson, 2022/03/03
- [PULL 13/30] tcg/i386: Implement avx512 variable rotate, Richard Henderson, 2022/03/03
- [PULL 20/30] tcg/i386: Implement more logical operations for avx512, Richard Henderson, 2022/03/03
- [PULL 18/30] tcg/i386: Implement avx512 min/max/abs, Richard Henderson, 2022/03/03
- [PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double, Richard Henderson, 2022/03/03
- [PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns, Richard Henderson, 2022/03/03
- [PULL 21/30] tcg/i386: Implement bitsel for avx512, Richard Henderson, 2022/03/03
- [PULL 28/30] tcg/mips: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03