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[PULL 13/30] tcg/i386: Implement avx512 variable rotate
From: |
Richard Henderson |
Subject: |
[PULL 13/30] tcg/i386: Implement avx512 variable rotate |
Date: |
Thu, 3 Mar 2022 10:59:27 -1000 |
AVX512VL has VPROLVD and VPRORVQ.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 25 ++++++++++++++++++++++++-
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 23a8b2a8c8..da1eff59aa 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -197,7 +197,7 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec have_avx512vl
#define TCG_TARGET_HAS_rots_vec 0
-#define TCG_TARGET_HAS_rotv_vec 0
+#define TCG_TARGET_HAS_rotv_vec have_avx512vl
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 3a9f6a3360..712ae3a168 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -420,6 +420,10 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
@@ -2839,6 +2843,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const umax_insn[4] = {
OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
};
+ static int const rotlv_insn[4] = {
+ OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ
+ };
+ static int const rotrv_insn[4] = {
+ OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ
+ };
static int const shlv_insn[4] = {
OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
};
@@ -2922,6 +2932,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sarv_vec:
insn = sarv_insn[vece];
goto gen_simd;
+ case INDEX_op_rotlv_vec:
+ insn = rotlv_insn[vece];
+ goto gen_simd;
+ case INDEX_op_rotrv_vec:
+ insn = rotrv_insn[vece];
+ goto gen_simd;
case INDEX_op_shls_vec:
insn = shls_insn[vece];
goto gen_simd;
@@ -3275,6 +3291,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_rotrv_vec:
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
@@ -3387,7 +3405,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
return 0;
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
- return have_avx2 && vece >= MO_32 ? -1 : 0;
+ switch (vece) {
+ case MO_32:
+ case MO_64:
+ return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
+ }
+ return 0;
case INDEX_op_mul_vec:
if (vece == MO_8) {
--
2.25.1
- [PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv, (continued)
- [PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv, Richard Henderson, 2022/03/03
- [PULL 04/30] tcg/ppc: Implement vector NAND, NOR, EQV, Richard Henderson, 2022/03/03
- [PULL 05/30] tcg/s390x: Implement vector NAND, NOR, EQV, Richard Henderson, 2022/03/03
- [PULL 07/30] tcg/i386: Add tcg_out_evex_opc, Richard Henderson, 2022/03/03
- [PULL 06/30] tcg/i386: Detect AVX512, Richard Henderson, 2022/03/03
- [PULL 08/30] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv, Richard Henderson, 2022/03/03
- [PULL 09/30] tcg/i386: Implement avx512 variable shifts, Richard Henderson, 2022/03/03
- [PULL 10/30] tcg/i386: Implement avx512 scalar shift, Richard Henderson, 2022/03/03
- [PULL 11/30] tcg/i386: Implement avx512 immediate sari shift, Richard Henderson, 2022/03/03
- [PULL 12/30] tcg/i386: Implement avx512 immediate rotate, Richard Henderson, 2022/03/03
- [PULL 13/30] tcg/i386: Implement avx512 variable rotate,
Richard Henderson <=
- [PULL 20/30] tcg/i386: Implement more logical operations for avx512, Richard Henderson, 2022/03/03
- [PULL 18/30] tcg/i386: Implement avx512 min/max/abs, Richard Henderson, 2022/03/03
- [PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double, Richard Henderson, 2022/03/03
- [PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns, Richard Henderson, 2022/03/03
- [PULL 21/30] tcg/i386: Implement bitsel for avx512, Richard Henderson, 2022/03/03
- [PULL 28/30] tcg/mips: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 26/30] linux-user: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 14/30] tcg/i386: Support avx512vbmi2 vector shift-double instructions, Richard Henderson, 2022/03/03
- [PULL 30/30] tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu, Richard Henderson, 2022/03/03