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[PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
From: |
Richard Henderson |
Subject: |
[PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu |
Date: |
Thu, 3 Mar 2022 10:59:38 -1000 |
When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
allow the 32-bit guest address to be sign extended within the
64-bit host register instead of zero extended.
This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
which naturally sign-extend 32-bit values, in contrast to x86_64
and AArch64 which zero-extend them.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 0e62aa5d7c..0dbc3efbc7 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -40,6 +40,7 @@
#include "qemu/plugin-memory.h"
#endif
#include "tcg/tcg-ldst.h"
+#include "tcg-target-sa32.h"
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
/* #define DEBUG_TLB */
@@ -93,6 +94,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
{
+ if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+ return tlb->addend + (int32_t)gaddr;
+ }
return tlb->addend + (uintptr_t)gaddr;
}
@@ -1244,7 +1248,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
vaddr,
desc->iotlb[index].attrs = attrs;
/* Now calculate the new entry */
- tn.addend = addend - vaddr_page;
+
+ if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+ tn.addend = addend - (int32_t)vaddr_page;
+ } else {
+ tn.addend = addend - vaddr_page;
+ }
+
if (prot & PAGE_READ) {
tn.addr_read = address;
if (wp_flags & BP_MEM_READ) {
--
2.25.1
- [PULL 13/30] tcg/i386: Implement avx512 variable rotate, (continued)
- [PULL 13/30] tcg/i386: Implement avx512 variable rotate, Richard Henderson, 2022/03/03
- [PULL 20/30] tcg/i386: Implement more logical operations for avx512, Richard Henderson, 2022/03/03
- [PULL 18/30] tcg/i386: Implement avx512 min/max/abs, Richard Henderson, 2022/03/03
- [PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double, Richard Henderson, 2022/03/03
- [PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns, Richard Henderson, 2022/03/03
- [PULL 21/30] tcg/i386: Implement bitsel for avx512, Richard Henderson, 2022/03/03
- [PULL 28/30] tcg/mips: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 26/30] linux-user: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 14/30] tcg/i386: Support avx512vbmi2 vector shift-double instructions, Richard Henderson, 2022/03/03
- [PULL 30/30] tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu,
Richard Henderson <=
- [PULL 22/30] tcg: Add TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 25/30] accel/tcg: Add guest_base_signed_addr32 for user-only, Richard Henderson, 2022/03/03
- [PULL 16/30] tcg/i386: Remove rotls_vec from tcg_target_op_def, Richard Henderson, 2022/03/03
- [PULL 29/30] tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 19/30] tcg/i386: Implement avx512 multiply, Richard Henderson, 2022/03/03
- [PULL 27/30] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2022/03/03
- [PULL 23/30] accel/tcg: Split out g2h_tlbe, Richard Henderson, 2022/03/03
- Re: [PULL 00/30] tcg patch queue, Peter Maydell, 2022/03/04