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[PULL 02/16] target/mips: Remove duplicated MIPSCPU::cp0_count_rate
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 02/16] target/mips: Remove duplicated MIPSCPU::cp0_count_rate |
Date: |
Mon, 7 Mar 2022 11:11:53 +0100 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <>20211213102340.1847248-1-f4bug@amsat.org>
---
target/mips/cpu.c | 10 ----------
target/mips/cpu.h | 9 ---------
target/mips/internal.h | 9 +++++++++
3 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0766e25693..af287177d5 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -434,13 +434,11 @@ static void mips_cpu_disas_set_info(CPUState *s,
disassemble_info *info)
* Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
*/
#define CPU_FREQ_HZ_DEFAULT 200000000
-#define CP0_COUNT_RATE_DEFAULT 2
static void mips_cp0_period_set(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
- /* env->CCRes isn't initialised this early, use env->cpu_model->CCRes. */
env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
env->cpu_model->CCRes);
assert(env->cp0_count_ns);
@@ -515,13 +513,6 @@ static ObjectClass *mips_cpu_class_by_name(const char
*cpu_model)
return oc;
}
-static Property mips_cpu_properties[] = {
- /* CP0 timer running at half the clock of the CPU */
- DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
- CP0_COUNT_RATE_DEFAULT),
- DEFINE_PROP_END_OF_LIST()
-};
-
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
@@ -561,7 +552,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
- device_class_set_props(dc, mips_cpu_properties);
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 56b1cbd091..ea66b866c6 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1168,7 +1168,6 @@ struct CPUMIPSState {
* @env: #CPUMIPSState
* @clock: this CPU input clock (may be connected
* to an output clock from another device).
- * @cp0_count_rate: rate at which the coprocessor 0 counter increments
*
* A MIPS CPU.
*/
@@ -1180,14 +1179,6 @@ struct MIPSCPU {
Clock *clock;
CPUNegativeOffsetState neg;
CPUMIPSState env;
- /*
- * The Count register acts as a timer, incrementing at a constant rate,
- * whether or not an instruction is executed, retired, or any forward
- * progress is made through the pipeline. The rate at which the counter
- * increments is implementation dependent, and is a function of the
- * pipeline clock of the processor, not the issue width of the processor.
- */
- unsigned cp0_count_rate;
};
diff --git a/target/mips/internal.h b/target/mips/internal.h
index daddb05fd4..1526fb880d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -46,6 +46,15 @@ struct mips_def_t {
target_ulong CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
int32_t SYNCI_Step;
+ /*
+ * @CCRes: rate at which the coprocessor 0 counter increments
+ *
+ * The Count register acts as a timer, incrementing at a constant rate,
+ * whether or not an instruction is executed, retired, or any forward
+ * progress is made through the pipeline. The rate at which the counter
+ * increments is implementation dependent, and is a function of the
+ * pipeline clock of the processor, not the issue width of the processor.
+ */
int32_t CCRes;
int32_t CP0_Status_rw_bitmask;
int32_t CP0_TCStatus_rw_bitmask;
--
2.34.1
- [PULL 00/16] MIPS patches for 2022-03-07, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 01/16] target/mips: Fix cycle counter timing calculations, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 02/16] target/mips: Remove duplicated MIPSCPU::cp0_count_rate,
Philippe Mathieu-Daudé <=
- [PULL 03/16] hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 04/16] malta: Move PCI interrupt handling from gt64xxx_pci to piix4, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 05/16] hw/isa/piix4: Resolve redundant i8259[] attribute, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 06/16] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq(), Philippe Mathieu-Daudé, 2022/03/07
- [PULL 07/16] hw/isa/piix4: Resolve global instance variable, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 08/16] hw/isa/piix4: Replace some magic IRQ constants, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 09/16] hw/mips/gt64xxx_pci: Resolve gt64120_register(), Philippe Mathieu-Daudé, 2022/03/07
- [PULL 10/16] hw/rtc/mc146818rtc: QOM'ify IRQ number, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 11/16] hw/rtc/m48t59-isa: QOM'ify IRQ number, Philippe Mathieu-Daudé, 2022/03/07
- [PULL 12/16] hw/input/pckbd: QOM'ify IRQ numbers, Philippe Mathieu-Daudé, 2022/03/07