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[PULL 09/18] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits a
From: |
Peter Maydell |
Subject: |
[PULL 09/18] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero |
Date: |
Mon, 7 Mar 2022 16:47:00 +0000 |
For VLD1/VST1 (single element to one lane) we are only accessing one
register, and so the 'stride' is meaningless. The bits that would
specify stride (insn bit [4] for size=1, bit [6] for size=2) are
specified to be zero in the encoding (which would correspond to a
stride of 1 for VLD2/VLD3/VLD4 etc), and we must UNDEF if they are
not.
We failed to make this check, which meant that we would incorrectly
handle some instruction patterns as loads or stores instead of
UNDEFing them. Enforce that stride == 1 for the nregs == 1 case.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/890
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303113741.2156877-2-peter.maydell@linaro.org
---
target/arm/translate-neon.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 3854dd35163..072fdc1e6ee 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -657,6 +657,9 @@ static bool trans_VLDST_single(DisasContext *s,
arg_VLDST_single *a)
/* Catch the UNDEF cases. This is unavoidably a bit messy. */
switch (nregs) {
case 1:
+ if (a->stride != 1) {
+ return false;
+ }
if (((a->align & (1 << a->size)) != 0) ||
(a->size == 2 && (a->align == 1 || a->align == 2))) {
return false;
--
2.25.1
- [PULL 00/18] target-arm queue, Peter Maydell, 2022/03/07
- [PULL 01/18] util: Make qemu_oom_check() a static function, Peter Maydell, 2022/03/07
- [PULL 02/18] util: Unify implementations of qemu_memalign(), Peter Maydell, 2022/03/07
- [PULL 03/18] util: Return valid allocation for qemu_try_memalign() with zero size, Peter Maydell, 2022/03/07
- [PULL 05/18] util: Share qemu_try_memalign() implementation between POSIX and Windows, Peter Maydell, 2022/03/07
- [PULL 04/18] meson.build: Don't misdetect posix_memalign() on Windows, Peter Maydell, 2022/03/07
- [PULL 07/18] util: Put qemu_vfree() in memalign.c, Peter Maydell, 2022/03/07
- [PULL 06/18] util: Use meson checks for valloc() and memalign() presence, Peter Maydell, 2022/03/07
- [PULL 09/18] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero,
Peter Maydell <=
- [PULL 08/18] osdep: Move memalign-related functions to their own header, Peter Maydell, 2022/03/07
- [PULL 10/18] target/arm/translate-neon: Simplify align field check for VLD3, Peter Maydell, 2022/03/07
- [PULL 11/18] hw/intc/arm_gicv3_its: Add trace events for commands, Peter Maydell, 2022/03/07
- [PULL 12/18] hw/intc/arm_gicv3_its: Add trace events for table reads and writes, Peter Maydell, 2022/03/07
- [PULL 13/18] hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps, Peter Maydell, 2022/03/07
- [PULL 14/18] hw/intc/arm_gicv3: Fix missing spaces in error log messages, Peter Maydell, 2022/03/07
- [PULL 15/18] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event, Peter Maydell, 2022/03/07
- [PULL 16/18] ui/cocoa: Use the standard about panel, Peter Maydell, 2022/03/07
- [PULL 17/18] target/arm: Provide cpu property for controling FEAT_LPA2, Peter Maydell, 2022/03/07
- [PULL 18/18] hw/arm/virt: Disable LPA2 for -machine virt-6.2, Peter Maydell, 2022/03/07