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[PULL 14/18] hw/intc/arm_gicv3: Fix missing spaces in error log messages
From: |
Peter Maydell |
Subject: |
[PULL 14/18] hw/intc/arm_gicv3: Fix missing spaces in error log messages |
Date: |
Mon, 7 Mar 2022 16:47:05 +0000 |
We forgot a space in some log messages, so the output ended
up looking like
gicv3_dist_write: invalid guest write at offset 0000000000008000size 8
with a missing space before "size". Add the missing spaces.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-5-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_dist.c | 4 ++--
hw/intc/arm_gicv3_its.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index 4164500ea96..28d913b2114 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -838,7 +838,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset,
uint64_t *data,
if (!r) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest read at offset " TARGET_FMT_plx
- "size %u\n", __func__, offset, size);
+ " size %u\n", __func__, offset, size);
trace_gicv3_dist_badread(offset, size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
* so use MEMTX_ERROR returns from leaf functions as a way to
@@ -879,7 +879,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset,
uint64_t data,
if (!r) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write at offset " TARGET_FMT_plx
- "size %u\n", __func__, offset, size);
+ " size %u\n", __func__, offset, size);
trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
* so use MEMTX_ERROR returns from leaf functions as a way to
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 9f4df6a8cbb..b96b874afdf 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -1313,7 +1313,7 @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr
offset, uint64_t *data,
if (!result) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest read at offset " TARGET_FMT_plx
- "size %u\n", __func__, offset, size);
+ " size %u\n", __func__, offset, size);
trace_gicv3_its_badread(offset, size);
/*
* The spec requires that reserved registers are RAZ/WI;
@@ -1349,7 +1349,7 @@ static MemTxResult gicv3_its_write(void *opaque, hwaddr
offset, uint64_t data,
if (!result) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write at offset " TARGET_FMT_plx
- "size %u\n", __func__, offset, size);
+ " size %u\n", __func__, offset, size);
trace_gicv3_its_badwrite(offset, data, size);
/*
* The spec requires that reserved registers are RAZ/WI;
--
2.25.1
- [PULL 05/18] util: Share qemu_try_memalign() implementation between POSIX and Windows, (continued)
- [PULL 05/18] util: Share qemu_try_memalign() implementation between POSIX and Windows, Peter Maydell, 2022/03/07
- [PULL 04/18] meson.build: Don't misdetect posix_memalign() on Windows, Peter Maydell, 2022/03/07
- [PULL 07/18] util: Put qemu_vfree() in memalign.c, Peter Maydell, 2022/03/07
- [PULL 06/18] util: Use meson checks for valloc() and memalign() presence, Peter Maydell, 2022/03/07
- [PULL 09/18] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero, Peter Maydell, 2022/03/07
- [PULL 08/18] osdep: Move memalign-related functions to their own header, Peter Maydell, 2022/03/07
- [PULL 10/18] target/arm/translate-neon: Simplify align field check for VLD3, Peter Maydell, 2022/03/07
- [PULL 11/18] hw/intc/arm_gicv3_its: Add trace events for commands, Peter Maydell, 2022/03/07
- [PULL 12/18] hw/intc/arm_gicv3_its: Add trace events for table reads and writes, Peter Maydell, 2022/03/07
- [PULL 13/18] hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps, Peter Maydell, 2022/03/07
- [PULL 14/18] hw/intc/arm_gicv3: Fix missing spaces in error log messages,
Peter Maydell <=
- [PULL 15/18] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event, Peter Maydell, 2022/03/07
- [PULL 16/18] ui/cocoa: Use the standard about panel, Peter Maydell, 2022/03/07
- [PULL 17/18] target/arm: Provide cpu property for controling FEAT_LPA2, Peter Maydell, 2022/03/07
- [PULL 18/18] hw/arm/virt: Disable LPA2 for -machine virt-6.2, Peter Maydell, 2022/03/07
- Re: [PULL 00/18] target-arm queue, Peter Maydell, 2022/03/08