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[PULL 15/18] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR re
From: |
Peter Maydell |
Subject: |
[PULL 15/18] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event |
Date: |
Mon, 7 Mar 2022 16:47:06 +0000 |
The trace_gicv3_icv_hppir_read trace event takes an integer value
which it uses to form the register name, which should be either
ICV_HPPIR0 or ICV_HPPIR1. We were passing in the 'grp' variable for
this, but that is either GICV3_G0 or GICV3_G1NS, which happen to be 0
and 2, which meant that tracing for the ICV_HPPIR1 register was
incorrectly printed as ICV_HPPIR2.
Use the same approach we do for all the other similar trace events,
and pass in 'ri->crm == 8 ? 0 : 1', deriving the index value
directly from the ARMCPRegInfo struct.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-6-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_cpuif.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index d7e03d0cab8..1a3d440a54b 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -612,7 +612,8 @@ static uint64_t icv_hppir_read(CPUARMState *env, const
ARMCPRegInfo *ri)
}
}
- trace_gicv3_icv_hppir_read(grp, gicv3_redist_affid(cs), value);
+ trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1,
+ gicv3_redist_affid(cs), value);
return value;
}
--
2.25.1
- [PULL 04/18] meson.build: Don't misdetect posix_memalign() on Windows, (continued)
- [PULL 04/18] meson.build: Don't misdetect posix_memalign() on Windows, Peter Maydell, 2022/03/07
- [PULL 07/18] util: Put qemu_vfree() in memalign.c, Peter Maydell, 2022/03/07
- [PULL 06/18] util: Use meson checks for valloc() and memalign() presence, Peter Maydell, 2022/03/07
- [PULL 09/18] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero, Peter Maydell, 2022/03/07
- [PULL 08/18] osdep: Move memalign-related functions to their own header, Peter Maydell, 2022/03/07
- [PULL 10/18] target/arm/translate-neon: Simplify align field check for VLD3, Peter Maydell, 2022/03/07
- [PULL 11/18] hw/intc/arm_gicv3_its: Add trace events for commands, Peter Maydell, 2022/03/07
- [PULL 12/18] hw/intc/arm_gicv3_its: Add trace events for table reads and writes, Peter Maydell, 2022/03/07
- [PULL 13/18] hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps, Peter Maydell, 2022/03/07
- [PULL 14/18] hw/intc/arm_gicv3: Fix missing spaces in error log messages, Peter Maydell, 2022/03/07
- [PULL 15/18] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event,
Peter Maydell <=
- [PULL 16/18] ui/cocoa: Use the standard about panel, Peter Maydell, 2022/03/07
- [PULL 17/18] target/arm: Provide cpu property for controling FEAT_LPA2, Peter Maydell, 2022/03/07
- [PULL 18/18] hw/arm/virt: Disable LPA2 for -machine virt-6.2, Peter Maydell, 2022/03/07
- Re: [PULL 00/18] target-arm queue, Peter Maydell, 2022/03/08