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[PULL 18/23] x86: add support for KVM_CAP_XSAVE2 and AMX state migration
From: |
Paolo Bonzini |
Subject: |
[PULL 18/23] x86: add support for KVM_CAP_XSAVE2 and AMX state migration |
Date: |
Mon, 7 Mar 2022 19:16:28 +0100 |
From: Jing Liu <jing2.liu@intel.com>
When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave
area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE
under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB.
Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-7-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.h | 4 ++++
target/i386/kvm/kvm.c | 42 ++++++++++++++++++++++++--------------
target/i386/xsave_helper.c | 28 +++++++++++++++++++++++++
3 files changed, 59 insertions(+), 15 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 925d0129e2..8c850e74b8 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1527,6 +1527,10 @@ typedef struct CPUX86State {
uint64_t opmask_regs[NB_OPMASK_REGS];
YMMReg zmmh_regs[CPU_NB_REGS];
ZMMReg hi16_zmm_regs[CPU_NB_REGS];
+#ifdef TARGET_X86_64
+ uint8_t xtilecfg[64];
+ uint8_t xtiledata[8192];
+#endif
/* sysenter registers */
uint32_t sysenter_cs;
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 385c5f8ed3..0fbdeacbb7 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -123,6 +123,7 @@ static uint32_t num_architectural_pmu_gp_counters;
static uint32_t num_architectural_pmu_fixed_counters;
static int has_xsave;
+static int has_xsave2;
static int has_xcrs;
static int has_pit_state2;
static int has_sregs2;
@@ -1586,6 +1587,26 @@ static Error *invtsc_mig_blocker;
#define KVM_MAX_CPUID_ENTRIES 100
+static void kvm_init_xsave(CPUX86State *env)
+{
+ if (has_xsave2) {
+ env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
+ } else if (has_xsave) {
+ env->xsave_buf_len = sizeof(struct kvm_xsave);
+ } else {
+ return;
+ }
+
+ env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
+ memset(env->xsave_buf, 0, env->xsave_buf_len);
+ /*
+ * The allocated storage must be large enough for all of the
+ * possible XSAVE state components.
+ */
+ assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
+ env->xsave_buf_len);
+}
+
int kvm_arch_init_vcpu(CPUState *cs)
{
struct {
@@ -1615,6 +1636,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
cpuid_i = 0;
+ has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
+
r = kvm_arch_set_tsc_khz(cs);
if (r < 0) {
return r;
@@ -2004,19 +2027,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (r) {
goto fail;
}
-
- if (has_xsave) {
- env->xsave_buf_len = sizeof(struct kvm_xsave);
- env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
- memset(env->xsave_buf, 0, env->xsave_buf_len);
-
- /*
- * The allocated storage must be large enough for all of the
- * possible XSAVE state components.
- */
- assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX)
- <= env->xsave_buf_len);
- }
+ kvm_init_xsave(env);
max_nested_state_len = kvm_max_nested_state_length();
if (max_nested_state_len > 0) {
@@ -3320,13 +3331,14 @@ static int kvm_get_xsave(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
void *xsave = env->xsave_buf;
- int ret;
+ int type, ret;
if (!has_xsave) {
return kvm_get_fpu(cpu);
}
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
+ type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
+ ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
if (ret < 0) {
return ret;
}
diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c
index ac61a96344..996e9f3bfe 100644
--- a/target/i386/xsave_helper.c
+++ b/target/i386/xsave_helper.c
@@ -126,6 +126,20 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf,
uint32_t buflen)
memcpy(pkru, &env->pkru, sizeof(env->pkru));
}
+
+ e = &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT];
+ if (e->size && e->offset) {
+ XSaveXTILECFG *tilecfg = buf + e->offset;
+
+ memcpy(tilecfg, &env->xtilecfg, sizeof(env->xtilecfg));
+ }
+
+ e = &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT];
+ if (e->size && e->offset && buflen >= e->size + e->offset) {
+ XSaveXTILEDATA *tiledata = buf + e->offset;
+
+ memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata));
+ }
#endif
}
@@ -247,5 +261,19 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void
*buf, uint32_t buflen)
pkru = buf + e->offset;
memcpy(&env->pkru, pkru, sizeof(env->pkru));
}
+
+ e = &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT];
+ if (e->size && e->offset) {
+ const XSaveXTILECFG *tilecfg = buf + e->offset;
+
+ memcpy(&env->xtilecfg, tilecfg, sizeof(env->xtilecfg));
+ }
+
+ e = &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT];
+ if (e->size && e->offset && buflen >= e->size + e->offset) {
+ const XSaveXTILEDATA *tiledata = buf + e->offset;
+
+ memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata));
+ }
#endif
}
--
2.34.1
- [PULL 05/23] qga/vss-win32: check old VSS SDK headers, (continued)
- [PULL 05/23] qga/vss-win32: check old VSS SDK headers, Paolo Bonzini, 2022/03/07
- [PULL 16/23] x86: Add XFD faulting bit for state components, Paolo Bonzini, 2022/03/07
- [PULL 17/23] x86: Add AMX CPUIDs enumeration, Paolo Bonzini, 2022/03/07
- [PULL 06/23] qga/vss: update informative message about MinGW, Paolo Bonzini, 2022/03/07
- [PULL 15/23] x86: Grant AMX permission for guest, Paolo Bonzini, 2022/03/07
- [PULL 08/23] kvm-irqchip: introduce new API to support route change, Paolo Bonzini, 2022/03/07
- [PULL 09/23] kvm/msi: do explicit commit when adding msi routes, Paolo Bonzini, 2022/03/07
- [PULL 10/23] target/i386: only include bits in pg_mode if they are not ignored, Paolo Bonzini, 2022/03/07
- [PULL 04/23] meson: fix generic location of vss headers, Paolo Bonzini, 2022/03/07
- [PULL 07/23] update meson-buildoptions.sh, Paolo Bonzini, 2022/03/07
- [PULL 18/23] x86: add support for KVM_CAP_XSAVE2 and AMX state migration,
Paolo Bonzini <=
- [PULL 13/23] x86: Fix the 64-byte boundary enumeration for extended state, Paolo Bonzini, 2022/03/07
- [PULL 03/23] vmxcap: Add 5-level EPT bit, Paolo Bonzini, 2022/03/07
- [PULL 02/23] whpx: Fixed incorrect CR8/TPR synchronization, Paolo Bonzini, 2022/03/07
- [PULL 12/23] linux-headers: include missing changes from 5.17, Paolo Bonzini, 2022/03/07
- [PULL 11/23] target/i386: Throw a #SS when loading a non-canonical IST, Paolo Bonzini, 2022/03/07
- [PULL 19/23] x86: Support XFD and AMX xsave data migration, Paolo Bonzini, 2022/03/07
- [PULL 14/23] x86: Add AMX XTILECFG and XTILEDATA components, Paolo Bonzini, 2022/03/07
- [PULL 22/23] check-block: revert TAP output and reintroduce -makecheck, Paolo Bonzini, 2022/03/07
- [PULL 01/23] whpx: Fixed reporting of the CPU context to GDB for 64-bit, Paolo Bonzini, 2022/03/07
- [PULL 23/23] gitlab-ci: do not run tests with address sanitizer, Paolo Bonzini, 2022/03/07