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[PULL 14/23] x86: Add AMX XTILECFG and XTILEDATA components
From: |
Paolo Bonzini |
Subject: |
[PULL 14/23] x86: Add AMX XTILECFG and XTILEDATA components |
Date: |
Mon, 7 Mar 2022 19:16:24 +0100 |
From: Jing Liu <jing2.liu@intel.com>
The AMX TILECFG register and the TMMx tile data registers are
saved/restored via XSAVE, respectively in state component 17
(64 bytes) and state component 18 (8192 bytes).
Add AMX feature bits to x86_ext_save_areas array to set
up AMX components. Add structs that define the layout of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-3-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 8 ++++++++
target/i386/cpu.h | 18 +++++++++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0f3c477dfc..ec35dd1717 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1402,6 +1402,14 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] =
{
[XSTATE_PKRU_BIT] =
{ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
.size = sizeof(XSavePKRU) },
+ [XSTATE_XTILE_CFG_BIT] = {
+ .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
+ .size = sizeof(XSaveXTILECFG),
+ },
+ [XSTATE_XTILE_DATA_BIT] = {
+ .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
+ .size = sizeof(XSaveXTILEDATA)
+ },
};
static uint32_t xsave_area_size(uint64_t mask)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7bd9d58505..3ff1b49d29 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -539,6 +539,8 @@ typedef enum X86Seg {
#define XSTATE_ZMM_Hi256_BIT 6
#define XSTATE_Hi16_ZMM_BIT 7
#define XSTATE_PKRU_BIT 9
+#define XSTATE_XTILE_CFG_BIT 17
+#define XSTATE_XTILE_DATA_BIT 18
#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
@@ -847,6 +849,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
/* AVX512_FP16 instruction */
#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
+/* AMX tile (two-dimensional register) */
+#define CPUID_7_0_EDX_AMX_TILE (1U << 24)
/* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */
@@ -1350,6 +1354,16 @@ typedef struct XSavePKRU {
uint32_t padding;
} XSavePKRU;
+/* Ext. save area 17: AMX XTILECFG state */
+typedef struct XSaveXTILECFG {
+ uint8_t xtilecfg[64];
+} XSaveXTILECFG;
+
+/* Ext. save area 18: AMX XTILEDATA state */
+typedef struct XSaveXTILEDATA {
+ uint8_t xtiledata[8][1024];
+} XSaveXTILEDATA;
+
QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
@@ -1357,6 +1371,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
+QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
+QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
typedef struct ExtSaveArea {
uint32_t feature, bits;
@@ -1364,7 +1380,7 @@ typedef struct ExtSaveArea {
uint32_t ecx;
} ExtSaveArea;
-#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1)
+#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
--
2.34.1
- [PULL 10/23] target/i386: only include bits in pg_mode if they are not ignored, (continued)
- [PULL 10/23] target/i386: only include bits in pg_mode if they are not ignored, Paolo Bonzini, 2022/03/07
- [PULL 04/23] meson: fix generic location of vss headers, Paolo Bonzini, 2022/03/07
- [PULL 07/23] update meson-buildoptions.sh, Paolo Bonzini, 2022/03/07
- [PULL 18/23] x86: add support for KVM_CAP_XSAVE2 and AMX state migration, Paolo Bonzini, 2022/03/07
- [PULL 13/23] x86: Fix the 64-byte boundary enumeration for extended state, Paolo Bonzini, 2022/03/07
- [PULL 03/23] vmxcap: Add 5-level EPT bit, Paolo Bonzini, 2022/03/07
- [PULL 02/23] whpx: Fixed incorrect CR8/TPR synchronization, Paolo Bonzini, 2022/03/07
- [PULL 12/23] linux-headers: include missing changes from 5.17, Paolo Bonzini, 2022/03/07
- [PULL 11/23] target/i386: Throw a #SS when loading a non-canonical IST, Paolo Bonzini, 2022/03/07
- [PULL 19/23] x86: Support XFD and AMX xsave data migration, Paolo Bonzini, 2022/03/07
- [PULL 14/23] x86: Add AMX XTILECFG and XTILEDATA components,
Paolo Bonzini <=
- [PULL 22/23] check-block: revert TAP output and reintroduce -makecheck, Paolo Bonzini, 2022/03/07
- [PULL 01/23] whpx: Fixed reporting of the CPU context to GDB for 64-bit, Paolo Bonzini, 2022/03/07
- [PULL 23/23] gitlab-ci: do not run tests with address sanitizer, Paolo Bonzini, 2022/03/07
- [PULL 21/23] KVM: SVM: always set MSR_AMD64_TSC_RATIO to default value, Paolo Bonzini, 2022/03/07
- [PULL 20/23] i386: Add Icelake-Server-v6 CPU model with 5-level EPT support, Paolo Bonzini, 2022/03/07
- Re: [PULL 00/23] QEMU changes for 7.0 soft freeze, Thomas Huth, 2022/03/08