Re: [PULL 00/61] target-arm queue

[Richard Henderson]

On 4/22/22 03:03, Peter Maydell wrote:
> This pullreq is (1) my GICv4 patches (2) most of the first third of RTH's
> cleanup patchset (3) one patch fixing an smmuv3 bug...
>
> thanks
> -- PMM
>
> The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f:
>
>    Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into 
> staging (2022-04-21 18:48:18 -0700)
>
> are available in the Git repository at:
>
>    https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20220422
>
> for you to fetch changes up to 9792130613191c1e0c34109918c5e07b9f1429a5:
>
>    hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
> smmuv3_translate() (2022-04-22 10:19:15 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>   * Implement GICv4 emulation
>   * Some cleanup patches in target/arm
>   * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
> smmuv3_translate()
>
> ----------------------------------------------------------------
> Peter Maydell (41):
>        hw/intc/arm_gicv3_its: Add missing blank line
>        hw/intc/arm_gicv3: Sanity-check num-cpu property
>        hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count
>        hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers
>        target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
>        hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"
>        hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4
>        hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI
>        hw/intc/arm_gicv3_its: Implement VMAPP
>        hw/intc/arm_gicv3_its: Distinguish success and error cases of 
> CMD_CONTINUE
>        hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"
>        hw/intc/arm_gicv3_its: Factor out CTE lookup sequence
>        hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt 
> code
>        hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()
>        hw/intc/arm_gicv3: Keep pointers to every connected ITS
>        hw/intc/arm_gicv3_its: Implement VMOVP
>        hw/intc/arm_gicv3_its: Implement VSYNC
>        hw/intc/arm_gicv3_its: Implement INV command properly
>        hw/intc/arm_gicv3_its: Implement INV for virtual interrupts
>        hw/intc/arm_gicv3_its: Implement VMOVI
>        hw/intc/arm_gicv3_its: Implement VINVALL
>        hw/intc/arm_gicv3: Implement GICv4's new redistributor frame
>        hw/intc/arm_gicv3: Implement new GICv4 redistributor registers
>        hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from 
> gicv3_cpuif_virt_update()
>        hw/intc/arm_gicv3_cpuif: Support vLPIs
>        hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily
>        hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic
>        hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic
>        hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes
>        hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code
>        hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()
>        hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()
>        hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling
>        hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()
>        hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()
>        hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()
>        hw/intc/arm_gicv3: Update ID and feature registers for GICv4
>        hw/intc/arm_gicv3: Allow 'revision' property to be set to 4
>        hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic()
>        hw/arm/virt: Abstract out calculation of redistributor region capacity
>        hw/arm/virt: Support TCG GICv4
>
> Richard Henderson (19):
>        target/arm: Update ISAR fields for ARMv8.8
>        target/arm: Update SCR_EL3 bits to ARMv8.8
>        target/arm: Update SCTLR bits to ARMv9.2
>        target/arm: Change DisasContext.aarch64 to bool
>        target/arm: Change CPUArchState.aarch64 to bool
>        target/arm: Extend store_cpu_offset to take field size
>        target/arm: Change DisasContext.thumb to bool
>        target/arm: Change CPUArchState.thumb to bool
>        target/arm: Remove fpexc32_access
>        target/arm: Split out set_btype_raw
>        target/arm: Split out gen_rebuild_hflags
>        target/arm: Simplify GEN_SHIFT in translate.c
>        target/arm: Simplify gen_sar
>        target/arm: Simplify aa32 DISAS_WFI
>        target/arm: Use tcg_constant in translate-m-nocp.c
>        target/arm: Use tcg_constant in translate-neon.c
>        target/arm: Use smin/smax for do_sat_addsub_32
>        target/arm: Use tcg_constant in translate-vfp.c
>        target/arm: Use tcg_constant_i32 in translate.h
>
> Xiang Chen (1):
>        hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
> smmuv3_translate()
>
>   docs/system/arm/virt.rst               |   5 +-
>   hw/intc/gicv3_internal.h               | 231 ++++++++-
>   include/hw/arm/virt.h                  |  19 +-
>   include/hw/intc/arm_gicv3_common.h     |  13 +
>   include/hw/intc/arm_gicv3_its_common.h |   1 +
>   target/arm/cpu.h                       |  59 ++-
>   target/arm/translate-a32.h             |  13 +-
>   target/arm/translate.h                 |  17 +-
>   hw/arm/smmuv3.c                        |   2 +-
>   hw/arm/virt.c                          | 102 +++-
>   hw/intc/arm_gicv3_common.c             |  54 +-
>   hw/intc/arm_gicv3_cpuif.c              | 195 ++++++--
>   hw/intc/arm_gicv3_dist.c               |   7 +-
>   hw/intc/arm_gicv3_its.c                | 876 +++++++++++++++++++++++++++------
>   hw/intc/arm_gicv3_its_kvm.c            |   2 +
>   hw/intc/arm_gicv3_kvm.c                |   5 +
>   hw/intc/arm_gicv3_redist.c             | 480 +++++++++++++++---
>   linux-user/arm/cpu_loop.c              |   2 +-
>   target/arm/cpu.c                       |  16 +-
>   target/arm/helper-a64.c                |   4 +-
>   target/arm/helper.c                    |  19 +-
>   target/arm/hvf/hvf.c                   |   2 +-
>   target/arm/m_helper.c                  |   6 +-
>   target/arm/op_helper.c                 |  13 -
>   target/arm/translate-a64.c             |  50 +-
>   target/arm/translate-m-nocp.c          |  12 +-
>   target/arm/translate-neon.c            |  21 +-
>   target/arm/translate-sve.c             |   9 +-
>   target/arm/translate-vfp.c             |  76 +--
>   target/arm/translate.c                 | 101 ++--
>   hw/intc/trace-events                   |  18 +-
>   31 files changed, 1890 insertions(+), 540 deletions(-)

Fails cross-arm64-system:

../hw/intc/arm_gicv3_its_kvm.c: In function ‘kvm_arm_its_realize’:
../hw/intc/arm_gicv3_its_kvm.c:109:5: error: implicit declaration of function 
‘gicv3_add_its’ [-Werror=implicit-function-declaration]
  109 |     gicv3_add_its(s->gicv3, dev);
      |     ^~~~~~~~~~~~~
../hw/intc/arm_gicv3_its_kvm.c:109:5: error: nested extern declaration of ‘gicv3_add_its’ 
[-Werror=nested-externs]
cc1: all warnings being treated as errors

https://gitlab.com/qemu-project/qemu/-/jobs/2365050344

r~