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[PULL 52/61] target/arm: Split out gen_rebuild_hflags
From: |
Peter Maydell |
Subject: |
[PULL 52/61] target/arm: Split out gen_rebuild_hflags |
Date: |
Fri, 22 Apr 2022 11:04:23 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
For aa32, the function has a parameter to use the new el.
For aa64, that never happens.
Use tcg_constant_i32 while we're at it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 21 +++++++++-----------
target/arm/translate.c | 40 +++++++++++++++++++++++---------------
2 files changed, 33 insertions(+), 28 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 13a3527345f..adbcd999415 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -341,6 +341,11 @@ static void a64_free_cc(DisasCompare64 *c64)
tcg_temp_free_i64(c64->value);
}
+static void gen_rebuild_hflags(DisasContext *s)
+{
+ gen_helper_rebuild_hflags_a64(cpu_env, tcg_constant_i32(s->current_el));
+}
+
static void gen_exception_internal(int excp)
{
TCGv_i32 tcg_excp = tcg_const_i32(excp);
@@ -1667,9 +1672,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
} else {
clear_pstate_bits(PSTATE_UAO);
}
- t1 = tcg_const_i32(s->current_el);
- gen_helper_rebuild_hflags_a64(cpu_env, t1);
- tcg_temp_free_i32(t1);
+ gen_rebuild_hflags(s);
break;
case 0x04: /* PAN */
@@ -1681,9 +1684,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
} else {
clear_pstate_bits(PSTATE_PAN);
}
- t1 = tcg_const_i32(s->current_el);
- gen_helper_rebuild_hflags_a64(cpu_env, t1);
- tcg_temp_free_i32(t1);
+ gen_rebuild_hflags(s);
break;
case 0x05: /* SPSel */
@@ -1741,9 +1742,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
} else {
clear_pstate_bits(PSTATE_TCO);
}
- t1 = tcg_const_i32(s->current_el);
- gen_helper_rebuild_hflags_a64(cpu_env, t1);
- tcg_temp_free_i32(t1);
+ gen_rebuild_hflags(s);
/* Many factors, including TCO, go into MTE_ACTIVE. */
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
} else if (dc_isar_feature(aa64_mte_insn_reg, s)) {
@@ -1990,9 +1989,7 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
* A write to any coprocessor regiser that ends a TB
* must rebuild the hflags for the next TB.
*/
- TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
- gen_helper_rebuild_hflags_a64(cpu_env, tcg_el);
- tcg_temp_free_i32(tcg_el);
+ gen_rebuild_hflags(s);
/*
* We default to ending the TB on a coprocessor register write,
* but allow this to be suppressed by the register definition
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1314406b193..4d7886fa853 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -351,6 +351,26 @@ void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
tcg_temp_free_i32(tmp_mask);
}
+static void gen_rebuild_hflags(DisasContext *s, bool new_el)
+{
+ bool m_profile = arm_dc_feature(s, ARM_FEATURE_M);
+
+ if (new_el) {
+ if (m_profile) {
+ gen_helper_rebuild_hflags_m32_newel(cpu_env);
+ } else {
+ gen_helper_rebuild_hflags_a32_newel(cpu_env);
+ }
+ } else {
+ TCGv_i32 tcg_el = tcg_constant_i32(s->current_el);
+ if (m_profile) {
+ gen_helper_rebuild_hflags_m32(cpu_env, tcg_el);
+ } else {
+ gen_helper_rebuild_hflags_a32(cpu_env, tcg_el);
+ }
+ }
+}
+
static void gen_exception_internal(int excp)
{
TCGv_i32 tcg_excp = tcg_const_i32(excp);
@@ -4885,17 +4905,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum,
int is64,
* A write to any coprocessor register that ends a TB
* must rebuild the hflags for the next TB.
*/
- TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- gen_helper_rebuild_hflags_m32(cpu_env, tcg_el);
- } else {
- if (ri->type & ARM_CP_NEWEL) {
- gen_helper_rebuild_hflags_a32_newel(cpu_env);
- } else {
- gen_helper_rebuild_hflags_a32(cpu_env, tcg_el);
- }
- }
- tcg_temp_free_i32(tcg_el);
+ gen_rebuild_hflags(s, ri->type & ARM_CP_NEWEL);
/*
* We default to ending the TB on a coprocessor register write,
* but allow this to be suppressed by the register definition
@@ -6445,7 +6455,7 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
tcg_temp_free_i32(addr);
tcg_temp_free_i32(reg);
/* If we wrote to CONTROL, the EL might have changed */
- gen_helper_rebuild_hflags_m32_newel(cpu_env);
+ gen_rebuild_hflags(s, true);
gen_lookup_tb(s);
return true;
}
@@ -8897,7 +8907,7 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
{
- TCGv_i32 tmp, addr, el;
+ TCGv_i32 tmp, addr;
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
return false;
@@ -8920,9 +8930,7 @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
gen_helper_v7m_msr(cpu_env, addr, tmp);
tcg_temp_free_i32(addr);
}
- el = tcg_const_i32(s->current_el);
- gen_helper_rebuild_hflags_m32(cpu_env, el);
- tcg_temp_free_i32(el);
+ gen_rebuild_hflags(s, false);
tcg_temp_free_i32(tmp);
gen_lookup_tb(s);
return true;
--
2.25.1
- [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool, (continued)
- [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2, Peter Maydell, 2022/04/22
- [PULL 46/61] target/arm: Change CPUArchState.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 47/61] target/arm: Extend store_cpu_offset to take field size, Peter Maydell, 2022/04/22
- [PULL 49/61] target/arm: Change CPUArchState.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 50/61] target/arm: Remove fpexc32_access, Peter Maydell, 2022/04/22
- [PULL 51/61] target/arm: Split out set_btype_raw, Peter Maydell, 2022/04/22
- [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c, Peter Maydell, 2022/04/22
- [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI, Peter Maydell, 2022/04/22
- [PULL 52/61] target/arm: Split out gen_rebuild_hflags,
Peter Maydell <=
- [PULL 48/61] target/arm: Change DisasContext.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 54/61] target/arm: Simplify gen_sar, Peter Maydell, 2022/04/22
- [PULL 56/61] target/arm: Use tcg_constant in translate-m-nocp.c, Peter Maydell, 2022/04/22
- [PULL 57/61] target/arm: Use tcg_constant in translate-neon.c, Peter Maydell, 2022/04/22
- [PULL 61/61] hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate(), Peter Maydell, 2022/04/22
- [PULL 58/61] target/arm: Use smin/smax for do_sat_addsub_32, Peter Maydell, 2022/04/22
- [PULL 41/61] hw/arm/virt: Support TCG GICv4, Peter Maydell, 2022/04/22
- [PULL 59/61] target/arm: Use tcg_constant in translate-vfp.c, Peter Maydell, 2022/04/22
- [PULL 60/61] target/arm: Use tcg_constant_i32 in translate.h, Peter Maydell, 2022/04/22
- Re: [PULL 00/61] target-arm queue, Richard Henderson, 2022/04/22