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[PULL 41/54] target/arm: Use tcg_constant in WHILE
From: |
Peter Maydell |
Subject: |
[PULL 41/54] target/arm: Use tcg_constant in WHILE |
Date: |
Thu, 28 Apr 2022 15:39:45 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 20 +++++++-------------
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 7a39ed0c062..727f5cca36f 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3568,7 +3568,7 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a)
static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
{
TCGv_i64 op0, op1, t0, t1, tmax;
- TCGv_i32 t2, t3;
+ TCGv_i32 t2;
TCGv_ptr ptr;
unsigned vsz = vec_full_reg_size(s);
unsigned desc = 0;
@@ -3624,7 +3624,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
}
}
- tmax = tcg_const_i64(vsz >> a->esz);
+ tmax = tcg_constant_i64(vsz >> a->esz);
if (eq) {
/* Equality means one more iteration. */
tcg_gen_addi_i64(t0, t0, 1);
@@ -3644,7 +3644,6 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
/* Bound to the maximum. */
tcg_gen_umin_i64(t0, t0, tmax);
- tcg_temp_free_i64(tmax);
/* Set the count to zero if the condition is false. */
tcg_gen_movi_i64(t1, 0);
@@ -3661,28 +3660,26 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
- t3 = tcg_const_i32(desc);
ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
if (a->lt) {
- gen_helper_sve_whilel(t2, ptr, t2, t3);
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
} else {
- gen_helper_sve_whileg(t2, ptr, t2, t3);
+ gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc));
}
do_pred_flags(t2);
tcg_temp_free_ptr(ptr);
tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
return true;
}
static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
{
TCGv_i64 op0, op1, diff, t1, tmax;
- TCGv_i32 t2, t3;
+ TCGv_i32 t2;
TCGv_ptr ptr;
unsigned vsz = vec_full_reg_size(s);
unsigned desc = 0;
@@ -3697,7 +3694,7 @@ static bool trans_WHILE_ptr(DisasContext *s,
arg_WHILE_ptr *a)
op0 = read_cpu_reg(s, a->rn, 1);
op1 = read_cpu_reg(s, a->rm, 1);
- tmax = tcg_const_i64(vsz);
+ tmax = tcg_constant_i64(vsz);
diff = tcg_temp_new_i64();
if (a->rw) {
@@ -3723,7 +3720,6 @@ static bool trans_WHILE_ptr(DisasContext *s,
arg_WHILE_ptr *a)
/* Bound to the maximum. */
tcg_gen_umin_i64(diff, diff, tmax);
- tcg_temp_free_i64(tmax);
/* Since we're bounded, pass as a 32-bit type. */
t2 = tcg_temp_new_i32();
@@ -3732,17 +3728,15 @@ static bool trans_WHILE_ptr(DisasContext *s,
arg_WHILE_ptr *a)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
- t3 = tcg_const_i32(desc);
ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
- gen_helper_sve_whilel(t2, ptr, t2, t3);
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
do_pred_flags(t2);
tcg_temp_free_ptr(ptr);
tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
return true;
}
--
2.25.1
- [PULL 12/54] target/arm: Use tcg_constant in disas_movw_imm, (continued)
- [PULL 12/54] target/arm: Use tcg_constant in disas_movw_imm, Peter Maydell, 2022/04/28
- [PULL 18/54] target/arm: Use tcg_constant in simd shift expanders, Peter Maydell, 2022/04/28
- [PULL 19/54] target/arm: Use tcg_constant in simd fp/int conversion, Peter Maydell, 2022/04/28
- [PULL 20/54] target/arm: Use tcg_constant in 2misc expanders, Peter Maydell, 2022/04/28
- [PULL 23/54] target/arm: Use tcg_constant for disas_iwmmxt_insn, Peter Maydell, 2022/04/28
- [PULL 22/54] target/arm: Use tcg_constant for aa32 exceptions, Peter Maydell, 2022/04/28
- [PULL 29/54] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32, Peter Maydell, 2022/04/28
- [PULL 17/54] target/arm: Use tcg_constant in disas_fp*, Peter Maydell, 2022/04/28
- [PULL 34/54] target/arm: Use tcg_constant in trans_CPS_v7m, Peter Maydell, 2022/04/28
- [PULL 35/54] target/arm: Use tcg_constant in trans_CSEL, Peter Maydell, 2022/04/28
- [PULL 41/54] target/arm: Use tcg_constant in WHILE,
Peter Maydell <=
- [PULL 37/54] target/arm: Use tcg_constant in SINCDEC, INCDEC, Peter Maydell, 2022/04/28
- [PULL 43/54] target/arm: Use tcg_constant in SUBR, Peter Maydell, 2022/04/28
- [PULL 44/54] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm, Peter Maydell, 2022/04/28
- [PULL 52/54] target/arm: Advertise support for FEAT_TTL, Peter Maydell, 2022/04/28
- [PULL 26/54] target/arm: Use tcg_constant for do_coproc_insn, Peter Maydell, 2022/04/28
- [PULL 39/54] target/arm: Use tcg_constant in {incr, wrap}_last_active, Peter Maydell, 2022/04/28
- [PULL 50/54] hw/arm/smmuv3: Cache event fault record, Peter Maydell, 2022/04/28
- [PULL 53/54] target/arm: Advertise support for FEAT_BBM level 2, Peter Maydell, 2022/04/28
- [PULL 32/54] target/arm: Use tcg_constant in LDM, STM, Peter Maydell, 2022/04/28
- [PULL 27/54] target/arm: Use tcg_constant for gen_srs, Peter Maydell, 2022/04/28