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Re: [PATCH v3 1/5] hw/char/pl011: refactor FIFO depth handling code
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 1/5] hw/char/pl011: refactor FIFO depth handling code |
Date: |
Fri, 20 Jan 2023 18:23:05 +0000 |
On Fri, 20 Jan 2023 at 15:54, Evgeny Iakovlev
<eiakovlev@linux.microsoft.com> wrote:
>
> PL011 can be in either of 2 modes depending guest config: FIFO and
> single register. The last mode could be viewed as a 1-element-deep FIFO.
>
> Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
> depth handling code to isolate calculating current FIFO depth.
>
> One functional (albeit guest-invisible) side-effect of this change is
> that previously we would always increment s->read_pos in UARTDR read
> handler even if FIFO was disabled, now we are limiting read_pos to not
> exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
>
> Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v3 0/5] Series of fixes for PL011 char device, Evgeny Iakovlev, 2023/01/20
- [PATCH v3 1/5] hw/char/pl011: refactor FIFO depth handling code, Evgeny Iakovlev, 2023/01/20
- [PATCH v3 3/5] hw/char/pl011: implement a reset method, Evgeny Iakovlev, 2023/01/20
- [PATCH v3 2/5] hw/char/pl011: add post_load hook for backwards-compatibility, Evgeny Iakovlev, 2023/01/20
- [PATCH v3 4/5] hw/char/pl011: better handling of FIFO flags on LCR reset, Evgeny Iakovlev, 2023/01/20
- [PATCH v3 5/5] hw/char/pl011: check if UART is enabled before RX or TX operation, Evgeny Iakovlev, 2023/01/20