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[Qemu-ppc] [PULL 30/43] target/ppc/POWER9: Direct all instr and data sto
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv |
Date: |
Wed, 22 Feb 2017 17:33:35 +1100 |
From: Suraj Jitindar Singh <address@hidden>
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/mmu-hash64.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c09255d..76669ed 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -652,7 +652,15 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState
*env,
if (msr_ir) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ break;
+ default:
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ break;
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HISI;
@@ -670,7 +678,15 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState
*env, uint64_t dar,
if (msr_dr) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ break;
+ default:
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ break;
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HDSI;
--
2.9.3
- [Qemu-ppc] [PULL 22/43] softfloat: Add round-to-odd rounding mode, (continued)
- [Qemu-ppc] [PULL 22/43] softfloat: Add round-to-odd rounding mode, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 12/43] target-ppc: implement load atomic instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 20/43] ppc4xx: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 19/43] mac99: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv,
David Gibson <=
- [Qemu-ppc] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 29/43] target/ppc/POWER9: Adapt LPCR handling for POWER9, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 36/43] change CPUArchId.cpu type to Object*, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 43/43] hw/ppc/ppc405_uc.c: Avoid integer overflows, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 41/43] target-ppc: fix Book-E TLB matching, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 42/43] hw/ppc/spapr: Check for valid page size when hot plugging memory, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 38/43] machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 21/43] spapr: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 34/43] pc: calculate topology only once when possible_cpus is initialised, David Gibson, 2017/02/22