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[Qemu-ppc] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define |
Date: |
Wed, 22 Feb 2017 17:33:32 +1100 |
From: Suraj Jitindar Singh <address@hidden>
The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bc2a2ce..bb96dd5 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -381,7 +381,7 @@ struct ppc_slb_t {
#define LPCR_ISL (1ull << (63 - 2))
#define LPCR_KBV (1ull << (63 - 3))
#define LPCR_DPFD_SHIFT (63 - 11)
-#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT)
+#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
#define LPCR_VRMASD_SHIFT (63 - 16)
#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
#define LPCR_RMLS_SHIFT (63 - 37)
--
2.9.3
- [Qemu-ppc] [PULL 15/43] target-ppc: add slbieg instruction, (continued)
- [Qemu-ppc] [PULL 15/43] target-ppc: add slbieg instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 14/43] target-ppc: generate exception for copy/paste, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 17/43] target-ppc: add wait instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 09/43] target-ppc: Add xsmaxcdp and xsmincdp instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 04/43] ppc: implement xsrqpi[x] instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 22/43] softfloat: Add round-to-odd rounding mode, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 12/43] target-ppc: implement load atomic instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 20/43] ppc4xx: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define,
David Gibson <=
- [Qemu-ppc] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 19/43] mac99: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 29/43] target/ppc/POWER9: Adapt LPCR handling for POWER9, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 36/43] change CPUArchId.cpu type to Object*, David Gibson, 2017/02/22