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Re: [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15 |
Date: |
Tue, 28 Feb 2017 10:21:54 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Mon, Feb 27, 2017 at 10:27:53AM +0530, Nikunj A Dadhania wrote:
> This series contains implentation of CA32 and OV32 bits added to the
> ISA 3.0. Various fixed-point arithmetic instructions are updated to take
> care of the newer flags.
>
> Finally the last patch adds new instruction mcrxrx, that helps reading
> the carry (CA and CA32) and the overflow (OV and OV32) flags
Applied to ppc-for-2.9, thanks.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 3/8] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 6/8] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 8/8] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 1/8] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 5/8] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 7/8] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 4/8] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 2/8] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/26
- Re: [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15,
David Gibson <=