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[PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction
From: |
frank . chang |
Subject: |
[PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction |
Date: |
Tue, 12 Jan 2021 17:39:05 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6b3caef1721..fae5ea3fa63 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -607,7 +607,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111
@r2_vm
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5b229d55307..6e45186b9b4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2989,12 +2989,18 @@ GEN_M_TRANS(vmsbf_m)
GEN_M_TRANS(vmsif_m)
GEN_M_TRANS(vmsof_m)
-/* Vector Iota Instruction */
+/*
+ * Vector Iota Instruction
+ *
+ * 1. The destination register cannot overlap the source register.
+ * 2. If masked, cannot overlap the mask register ('v0').
+ * 3. An illegal instruction exception is raised if vstart is non-zero.
+ */
static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s) &&
- require_noover(a->rd, s->lmul, a->rs2, 0) &&
+ !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
require_vm(a->vm, a->rd) &&
require_align(a->rd, s->lmul)) {
uint32_t data = 0;
--
2.17.1
- Re: [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, (continued)
- [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations, frank . chang, 2021/01/12
- [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/01/12
- [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/01/12
- [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/01/12
- [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/01/12
- [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/01/12
- [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction,
frank . chang <=
- [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/01/12
- [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/01/12
- [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/01/12
- [PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/01/12
- [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/01/12
- [PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/01/12
- [PATCH v6 38/72] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/01/12
- [PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/01/12