Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl

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Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl

From:	Weiwei Li
Subject:	Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl
Date:	Sun, 20 Mar 2022 12:59:29 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0


在 2022/3/12 下午2:28, ~eopxd 写道:

From: eopXD <eop.chen@sifive.com>

According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
  target/riscv/insn_trans/trans_rvv.c.inc | 30 +++++++++++++++++++++++++
  1 file changed, 30 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 275fded6e4..3ae75dc6ae 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc

@@ -3164,6 +3189,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          gen_helper_gvec_3_ptr *fn = gen_helper_##NAME;             \
          TCGLabel *over = gen_new_label();                          \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -3201,6 +3227,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, a->vm);

          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);

@@ -3674,6 +3702,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
          };
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, LMUL, s->lmul);

          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),

vmsbf.m, vmsif.m,vmsof.m, viota.m, vcompress require vstart to bezero. so these checks seem unnecessary.


Regards,

Weiwei Li

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[PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions, ~eopxd, 2022/03/19
- [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl, Weiwei Li, 2022/03/19
  - Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl, Weiwei Li <=
- [PATCH qemu 01/13] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 01/13] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, Weiwei Li, 2022/03/19
- [PATCH qemu 04/13] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 04/13] target/riscv: rvv: Add tail agnostic for vv instructions, Weiwei Li, 2022/03/19
- [PATCH qemu 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Weiwei Li, 2022/03/19
- [PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Weiwei Li, 2022/03/19
- [PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, Weiwei Li, 2022/03/19

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