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[PATCH v2 12/43] hw/isa/piix3: Create USB controller in host device
From: |
Bernhard Beschow |
Subject: |
[PATCH v2 12/43] hw/isa/piix3: Create USB controller in host device |
Date: |
Sat, 22 Oct 2022 17:04:37 +0200 |
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/i386/pc_piix.c | 7 ++-----
hw/isa/Kconfig | 1 +
hw/isa/piix3.c | 17 +++++++++++++++++
include/hw/southbridge/piix.h | 4 ++++
4 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index b97bff5674..22c1c5404c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -51,7 +51,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -221,6 +220,8 @@ static void pc_init1(MachineState *machine,
pcms->bus = pci_bus;
pci_dev = pci_new_multifunction(-1, true, type);
+ object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), &error_abort);
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
piix3->pic = x86ms->gsi;
@@ -299,10 +300,6 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && machine_usb(machine)) {
- pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
- }
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 6e8f9cac54..f02eca3c3e 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -36,6 +36,7 @@ config PIIX3
select I8257
select ISA_BUS
select MC146818RTC
+ select USB_UHCI
config PIIX4
bool
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 75c6370e33..2f227fde0e 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -300,6 +300,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
@@ -320,6 +321,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
return;
}
+
+ /* USB */
+ if (d->has_usb) {
+ object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
+ TYPE_PIIX3_USB_UHCI);
+ qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -342,6 +353,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
}
+static Property pci_piix3_props[] = {
+ DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -361,6 +377,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b1fa08dd2b..5367917182 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -54,12 +55,15 @@ struct PIIXState {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
RTCState rtc;
+ UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+ bool has_usb;
};
typedef struct PIIXState PIIX3State;
--
2.38.1
- [PATCH v2 04/43] hw/isa/piix3: Add size constraints to rcr_ops, (continued)
- [PATCH v2 04/43] hw/isa/piix3: Add size constraints to rcr_ops, Bernhard Beschow, 2022/10/22
- [PATCH v2 05/43] hw/isa/piix3: Modernize reset handling, Bernhard Beschow, 2022/10/22
- [PATCH v2 06/43] hw/isa/piix3: Prefer pci_address_space() over get_system_memory(), Bernhard Beschow, 2022/10/22
- [PATCH v2 07/43] hw/isa/piix4: Rename wrongly named method, Bernhard Beschow, 2022/10/22
- [PATCH v2 08/43] hw/ide/piix: Introduce TYPE_ macros for PIIX IDE controllers, Bernhard Beschow, 2022/10/22
- [PATCH v2 09/43] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models, Bernhard Beschow, 2022/10/22
- [PATCH v2 10/43] hw/i386/pc: Create RTC controllers in south bridges, Bernhard Beschow, 2022/10/22
- [PATCH v2 11/43] hw/i386/pc: No need for rtc_state to be an out-parameter, Bernhard Beschow, 2022/10/22
- [PATCH v2 12/43] hw/isa/piix3: Create USB controller in host device,
Bernhard Beschow <=
- [PATCH v2 13/43] hw/isa/piix3: Create power management controller in host device, Bernhard Beschow, 2022/10/22
- [PATCH v2 14/43] hw/intc/i8259: Introduce i8259 proxy "isa-pic", Bernhard Beschow, 2022/10/22
- [PATCH v2 15/43] hw/isa/piix3: Create ISA PIC in host device, Bernhard Beschow, 2022/10/22
- [PATCH v2 16/43] hw/isa/piix3: Create IDE controller in host device, Bernhard Beschow, 2022/10/22
- [PATCH v2 17/43] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2022/10/22
- [PATCH v2 18/43] hw/isa/piix3: Remove unused include, Bernhard Beschow, 2022/10/22
- [PATCH v2 19/43] hw/isa/piix3: Allow board to provide PCI interrupt routes, Bernhard Beschow, 2022/10/22