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Re: [Qemu-devel] Help on TLB Flush

From: Peter Maydell
Subject: Re: [Qemu-devel] Help on TLB Flush
Date: Thu, 12 Feb 2015 22:02:29 +0000

On 12 February 2015 at 15:38, Alexander Graf <address@hidden> wrote:
> On 12.02.15 15:58, Peter Maydell wrote:
>> All ARM TLB maintenance operations have both "this CPU only"
>> and "all TLBs in the Inner Shareable domain" [that's ARM-speak
>> for "every CPU core in the cluster"] variants (the latter
>> being the TLB *IS operations). Looking at Linux's
>> arch/arm64/mm/tlb.S and arch/arm64/include/asm/tlbflush.h
>> most of the operations defined there use the IS variants.
> Wow, did anyone benchmark this? I know that PPC switched away from
> global flushes and instead tracks the CPUs a task was running on to
> limit the scope of CPUs that need to flush.

That would be a valid implementation. The CPU has to behave
as the spec says it must, but there's no reason you couldn't
implement "flush by ASID for all TLBs" via some implementation
specific tracking of ASID use per CPU to limit which cores
you sent the flush request to, if you thought that was a
better way to do it.

-- PMM

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