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[Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGC
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same |
Date: |
Fri, 13 Oct 2017 17:24:30 +0100 |
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/helper-a64.c | 14 +++++++-------
target/arm/helper-a64.h | 1 -
target/arm/translate-a64.c | 3 +++
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index b62d77aec4..137866732d 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -609,10 +609,10 @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b,
void *fpstp)
return -float16_le(f1, f0, fpst);
}
-/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */
-/* { */
-/* float_status *fpst = fpstp; */
-/* float16 f0 = float16_abs(a); */
-/* float16 f1 = float16_abs(b); */
-/* return -float16_lt(f1, f0, fpst); */
-/* } */
+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ float16 f0 = float16_abs(a);
+ float16 f1 = float16_abs(b);
+ return -float16_lt(f1, f0, fpst);
+}
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 952869f43e..66c4062ea5 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -53,7 +53,6 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
-
DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 623b0b3fab..4ad470d9e8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9819,6 +9819,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext
*s, uint32_t insn)
case 0x27: /* FDIV */
gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
break;
+ case 0x35: /* FACGT */
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
default:
fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
__func__, insn, fpopcode, s->pc);
--
2.14.1
- Re: [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix, (continued)
- [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same,
Alex Bennée <=
- [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK), Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int, Alex Bennée, 2017/10/13