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[Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scala
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode |
Date: |
Fri, 13 Oct 2017 17:24:21 +0100 |
This is the initial decode skeleton for the Advanced SIMD scalar
three same instruction group. The fprintf is purely to aid debugging
as the additional instructions are added. It will be removed once the
group is complete.
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/translate-a64.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 50e53bf8b0..5e531b3ae4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9751,6 +9751,81 @@ static void disas_simd_three_reg_same(DisasContext *s,
uint32_t insn)
}
}
+/*
+ * Advanced SIMD three same (ARMv8.2 FP16 variants)
+ *
+ * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
+ * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
+ *
+ * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
+ * (register), FACGE, FABD, FCMGT (register) and FACGT.
+ *
+ */
+static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
+{
+ int opcode, fpopcode;
+ int is_q, u, a, rm, rn, rd;
+ int datasize, elements;
+ int pass;
+ TCGv_ptr fpst;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (!fp_access_check(s)) {
+ return;
+ }
+
+ /* For these floating point ops, the U, a and opcode bits
+ * together indicate the operation.
+ */
+ opcode = extract32(insn, 11, 3);
+ u = extract32(insn, 29, 1);
+ a = extract32(insn, 23, 1);
+ is_q = extract32(insn, 30, 1);
+ rm = extract32(insn, 16, 5);
+ rn = extract32(insn, 5, 5);
+ rd = extract32(insn, 0, 5);
+
+ fpopcode = opcode | (a << 4) | (u << 5);
+ datasize = is_q ? 128 : 64;
+ elements = datasize / 16;
+
+ fpst = get_fpstatus_ptr();
+
+ for (pass = 0; pass < elements; pass++) {
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+ TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
+
+ switch (fpopcode) {
+ default:
+ fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn,
fpopcode);
+ g_assert_not_reached();
+ }
+
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+ tcg_temp_free_i32(tcg_res);
+ tcg_temp_free_i32(tcg_op1);
+ tcg_temp_free_i32(tcg_op2);
+ }
+
+ tcg_temp_free_ptr(fpst);
+
+ if (!is_q) {
+ /* non-quad vector op */
+ clear_vec_high(s, rd);
+ }
+
+}
+
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
int size, int rn, int rd)
{
@@ -11159,6 +11234,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x4e280800, 0xff3e0c00, disas_crypto_aes },
{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
+ { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
{ 0x00000000, 0x00000000, NULL }
};
--
2.14.1
- [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support, (continued)
- [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode,
Alex Bennée <=
- [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK), Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion, Alex Bennée, 2017/10/13