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[Qemu-devel] [PATCH v5 46/76] target/mips: Add updating BadInstr, BadIns
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 46/76] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS |
Date: |
Mon, 30 Jul 2018 18:12:19 +0200 |
From: Stefan Markovic <address@hidden>
Update BadInstr, BadInstrP,and BadInstrX registers for nanoMIPS.
The same support for pre-nanoMIPS remains unimplemented.
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/helper.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index e215af9..b25e000 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -682,6 +682,31 @@ static void set_hflags_for_handler (CPUMIPSState *env)
static inline void set_badinstr_registers(CPUMIPSState *env)
{
+ if (env->insn_flags & ISA_NANOMIPS32) {
+ if (env->CP0_Config3 & (1 << CP0C3_BI)) {
+ uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
+ if ((instr & 0x10000000) == 0) {
+ instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
+ }
+ env->CP0_BadInstr = instr;
+
+ if ((instr & 0xFC000000) == 0x60000000) {
+ instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
+ env->CP0_BadInstrX = instr;
+ }
+ }
+ if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
+ (env->hflags & MIPS_HFLAG_BMASK)) {
+ if (!(env->hflags & MIPS_HFLAG_B16)) {
+ env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
+ } else {
+ env->CP0_BadInstrP =
+ (cpu_lduw_code(env, env->active_tc.PC - 2)) << 16;
+ }
+ }
+ return;
+ }
+
if (env->hflags & MIPS_HFLAG_M16) {
/* TODO: add BadInstr support for microMIPS */
return;
--
2.7.4
- Re: [Qemu-devel] [PATCH v5 41/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, (continued)
- [Qemu-devel] [PATCH v5 42/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 44/76] target/mips: Add handling of branch delay slots for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 45/76] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 46/76] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 47/76] target/mips: Implement CP0 Config0.WR bit functionality, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 48/76] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 49/76] target/mips: Adjust exception_resume_pc() for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 50/76] target/mips: Adjust set_hflags_for_handler() for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 51/76] target/mips: Adjust set_pc() for nanoMIPS, Aleksandar Markovic, 2018/07/30