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Re: [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE

From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
Date: Tue, 31 Jul 2018 14:58:40 -0400
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1

On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +        switch (extract32(ctx->opcode, 12, 1)) {
> +        case 0:
> +            /* NM_SHRA_QB */
> +            check_dspr2(ctx);
> +            gen_helper_shra_qb(cpu_gpr[ret], t0, v1_t);
More unprotected use of cpu_gpr[0].

I think you need some sort of solution that prevents this completely, without
having to think about it.  E.g. global replace cpu_gpr[x] -> read_gpr(ctx, x) /
dest_gpr(ctx, x), where the two functions allocate tcg temporaries on demand.

I think the model used in target/alpha/translate.c is ideal.  However, there
are variations on this theme in target/arm/translate-a64.c,
target/sparc/translate.c, and target/openrisc/translate.c.


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