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Re: [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6 |
Date: |
Tue, 31 Jul 2018 14:58:40 -0400 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> + switch (extract32(ctx->opcode, 12, 1)) {
> + case 0:
> + /* NM_SHRA_QB */
> + check_dspr2(ctx);
> + gen_helper_shra_qb(cpu_gpr[ret], t0, v1_t);
More unprotected use of cpu_gpr[0].
I think you need some sort of solution that prevents this completely, without
having to think about it. E.g. global replace cpu_gpr[x] -> read_gpr(ctx, x) /
dest_gpr(ctx, x), where the two functions allocate tcg temporaries on demand.
I think the model used in target/alpha/translate.c is ideal. However, there
are variations on this theme in target/arm/translate-a64.c,
target/sparc/translate.c, and target/openrisc/translate.c.
r~
- Re: [Qemu-devel] [PATCH v5 38/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, (continued)
- [Qemu-devel] [PATCH v5 39/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 40/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 41/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 42/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/07/30
- Re: [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 44/76] target/mips: Add handling of branch delay slots for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 45/76] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 46/76] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 47/76] target/mips: Implement CP0 Config0.WR bit functionality, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 48/76] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS, Aleksandar Markovic, 2018/07/30