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Re: [Qemu-devel] [PATCH v5 41/76] target/mips: Add emulation of DSP ASE
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v5 41/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4 |
Date: |
Tue, 31 Jul 2018 14:50:02 -0400 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
+static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
> + int ret, int v1, int v2)
> +{
> + TCGv t0;
> + TCGv t1;
> +
> + TCGv v0_t;
> + TCGv v1_t;
> +
> + t0 = tcg_temp_new();
> + t1 = tcg_temp_new();
> +
> + v0_t = tcg_temp_new();
> + v1_t = tcg_temp_new();
> +
> + gen_load_gpr(v0_t, ret);
> + gen_load_gpr(v1_t, v1);
> +
> + switch (opc) {
> + case NM_POOL32AXF_2_0_7:
> + switch (extract32(ctx->opcode, 9, 3)) {
> + case NM_DPA_W_PH:
> + case NM_DPAQ_S_W_PH:
> + case NM_DPS_W_PH:
> + case NM_DPSQ_S_W_PH:
> + gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2);
This structure, in which you have loaded gpr values, then discard them only to
load them up again in a different helper function, could use some improvement.
> + case NM_BALIGN:
> + gen_load_gpr(t0, v1);
> + v2 &= 3;
> + if (v2 != 0 && v2 != 2) {
> + tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * v2);
More unprotected uses of cpu_gpr[0].
r~
- [Qemu-devel] [PATCH v5 36/76] target/mips: Add emulation of nanoMIPS 32-bit branch instructions, (continued)
- [Qemu-devel] [PATCH v5 36/76] target/mips: Add emulation of nanoMIPS 32-bit branch instructions, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 37/76] target/mips: Implement MT ASE support for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 38/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 39/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 40/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 41/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Aleksandar Markovic, 2018/07/30
- Re: [Qemu-devel] [PATCH v5 41/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 42/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 43/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 44/76] target/mips: Add handling of branch delay slots for nanoMIPS, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 45/76] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/07/30
- [Qemu-devel] [PATCH v5 46/76] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/07/30