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[PULL 14/37] hw/timer/cadence_ttc: move timer_new from init() into reali
From: |
Peter Maydell |
Subject: |
[PULL 14/37] hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid memleaks |
Date: |
Thu, 5 Mar 2020 16:30:37 +0000 |
From: Pan Nengyuan <address@hidden>
There are some memleaks when we call 'device_list_properties'. This patch move
timer_new from init into realize to fix it.
Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/timer/cadence_ttc.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
index 5e3128c1e37..b0ba6b2bbae 100644
--- a/hw/timer/cadence_ttc.c
+++ b/hw/timer/cadence_ttc.c
@@ -412,18 +412,23 @@ static void cadence_timer_init(uint32_t freq,
CadenceTimerState *s)
static void cadence_ttc_init(Object *obj)
{
CadenceTTCState *s = CADENCE_TTC(obj);
- int i;
-
- for (i = 0; i < 3; ++i) {
- cadence_timer_init(133000000, &s->timer[i]);
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->timer[i].irq);
- }
memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s,
"timer", 0x1000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
}
+static void cadence_ttc_realize(DeviceState *dev, Error **errp)
+{
+ CadenceTTCState *s = CADENCE_TTC(dev);
+ int i;
+
+ for (i = 0; i < 3; ++i) {
+ cadence_timer_init(133000000, &s->timer[i]);
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->timer[i].irq);
+ }
+}
+
static int cadence_timer_pre_save(void *opaque)
{
cadence_timer_sync((CadenceTimerState *)opaque);
@@ -479,6 +484,7 @@ static void cadence_ttc_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_cadence_ttc;
+ dc->realize = cadence_ttc_realize;
}
static const TypeInfo cadence_ttc_info = {
--
2.20.1
- [PULL 32/37] target/arm: Optimize cpu_mmu_index, (continued)
- [PULL 32/37] target/arm: Optimize cpu_mmu_index, Peter Maydell, 2020/03/05
- [PULL 33/37] target/arm: Introduce core_to_aa64_mmu_idx, Peter Maydell, 2020/03/05
- [PULL 20/37] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Peter Maydell, 2020/03/05
- [PULL 23/37] target/arm: Honor the HCR_EL2.TPCP bit, Peter Maydell, 2020/03/05
- [PULL 37/37] target/arm: Clean address for DC ZVA, Peter Maydell, 2020/03/05
- [PULL 35/37] target/arm: Move helper_dc_zva to helper-a64.c, Peter Maydell, 2020/03/05
- [PULL 01/37] hw/arm: versal: Add support for the LPD ADMAs, Peter Maydell, 2020/03/05
- [PULL 07/37] hw/arm/mainstone: Simplify since the machines are little-endian only, Peter Maydell, 2020/03/05
- [PULL 13/37] hw/arm/strongarm: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 12/37] hw/arm/spitz: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 14/37] hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid memleaks,
Peter Maydell <=
- [PULL 17/37] target/arm: Disable has_el2 and has_el3 for user-only, Peter Maydell, 2020/03/05
- [PULL 19/37] target/arm: Improve masking in arm_hcr_el2_eff, Peter Maydell, 2020/03/05
- [PULL 28/37] hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8, Peter Maydell, 2020/03/05
- Re: [PULL 00/37] target-arm queue, Peter Maydell, 2020/03/05