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[PULL 17/37] target/arm: Disable has_el2 and has_el3 for user-only
From: |
Peter Maydell |
Subject: |
[PULL 17/37] target/arm: Disable has_el2 and has_el3 for user-only |
Date: |
Thu, 5 Mar 2020 16:30:40 +0000 |
From: Richard Henderson <address@hidden>
In arm_cpu_reset, we configure many system registers so that user-only
behaves as it should with a minimum of ifdefs. However, we do not set
all of the system registers as required for a cpu with EL2 and EL3.
Disabling EL2 and EL3 mean that we will not look at those registers,
which means that we don't have to worry about configuring them.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index de00a45e903..185a46f5abd 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1103,11 +1103,13 @@ static Property arm_cpu_reset_hivecs_property =
static Property arm_cpu_rvbar_property =
DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
+#ifndef CONFIG_USER_ONLY
static Property arm_cpu_has_el2_property =
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
static Property arm_cpu_has_el3_property =
DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
+#endif
static Property arm_cpu_cfgend_property =
DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
@@ -1222,25 +1224,25 @@ void arm_cpu_post_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
}
+#ifndef CONFIG_USER_ONLY
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
/* Add the has_el3 state CPU property only if EL3 is allowed. This
will
* prevent "has_el3" from existing on CPUs which cannot support EL3.
*/
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
-#ifndef CONFIG_USER_ONLY
object_property_add_link(obj, "secure-memory",
TYPE_MEMORY_REGION,
(Object **)&cpu->secure_memory,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG,
&error_abort);
-#endif
}
if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
}
+#endif
if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
cpu->has_pmu = true;
--
2.20.1
- [PULL 33/37] target/arm: Introduce core_to_aa64_mmu_idx, (continued)
- [PULL 33/37] target/arm: Introduce core_to_aa64_mmu_idx, Peter Maydell, 2020/03/05
- [PULL 20/37] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Peter Maydell, 2020/03/05
- [PULL 23/37] target/arm: Honor the HCR_EL2.TPCP bit, Peter Maydell, 2020/03/05
- [PULL 37/37] target/arm: Clean address for DC ZVA, Peter Maydell, 2020/03/05
- [PULL 35/37] target/arm: Move helper_dc_zva to helper-a64.c, Peter Maydell, 2020/03/05
- [PULL 01/37] hw/arm: versal: Add support for the LPD ADMAs, Peter Maydell, 2020/03/05
- [PULL 07/37] hw/arm/mainstone: Simplify since the machines are little-endian only, Peter Maydell, 2020/03/05
- [PULL 13/37] hw/arm/strongarm: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 12/37] hw/arm/spitz: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 14/37] hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 17/37] target/arm: Disable has_el2 and has_el3 for user-only,
Peter Maydell <=
- [PULL 19/37] target/arm: Improve masking in arm_hcr_el2_eff, Peter Maydell, 2020/03/05
- [PULL 28/37] hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8, Peter Maydell, 2020/03/05
- Re: [PULL 00/37] target-arm queue, Peter Maydell, 2020/03/05