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[PULL 19/31] Cadence: gem: fix wraparound in 64bit descriptors
From: |
Peter Maydell |
Subject: |
[PULL 19/31] Cadence: gem: fix wraparound in 64bit descriptors |
Date: |
Thu, 30 Apr 2020 12:51:30 +0100 |
From: Ramon Fried <address@hidden>
Wraparound of TX descriptor cyclic buffer only updated
the low 32 bits of the descriptor.
Fix that by checking if we're working with 64bit descriptors.
Signed-off-by: Ramon Fried <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/net/cadence_gem.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 51ec5a072d0..b7b7985bf26 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1238,7 +1238,14 @@ static void gem_transmit(CadenceGEMState *s)
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
tx_desc_set_last(desc);
- packet_desc_addr = s->regs[GEM_TXQBASE];
+
+ if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ packet_desc_addr = s->regs[GEM_TBQPH];
+ packet_desc_addr <<= 32;
+ } else {
+ packet_desc_addr = 0;
+ }
+ packet_desc_addr |= s->regs[GEM_TXQBASE];
} else {
packet_desc_addr += 4 * gem_get_desc_len(s, false);
}
--
2.20.1
- [PULL 08/31] tests/boot_linux_console: Add ethernet test to SmartFusion2, (continued)
- [PULL 08/31] tests/boot_linux_console: Add ethernet test to SmartFusion2, Peter Maydell, 2020/04/30
- [PULL 10/31] hw/core/clock-vmstate: define a vmstate entry for clock state, Peter Maydell, 2020/04/30
- [PULL 11/31] qdev: add clock input&output support to devices., Peter Maydell, 2020/04/30
- [PULL 12/31] qdev-clock: introduce an init array to ease the device construction, Peter Maydell, 2020/04/30
- [PULL 09/31] hw/core/clock: introduce clock object, Peter Maydell, 2020/04/30
- [PULL 13/31] docs/clocks: add device's clock documentation, Peter Maydell, 2020/04/30
- [PULL 14/31] hw/misc/zynq_slcr: add clock generation for uarts, Peter Maydell, 2020/04/30
- [PULL 16/31] hw/arm/xilinx_zynq: connect uart clocks to slcr, Peter Maydell, 2020/04/30
- [PULL 15/31] hw/char/cadence_uart: add clock support, Peter Maydell, 2020/04/30
- [PULL 18/31] hw/arm: versal: Setup the ADMA with 128bit bus-width, Peter Maydell, 2020/04/30
- [PULL 19/31] Cadence: gem: fix wraparound in 64bit descriptors,
Peter Maydell <=
- [PULL 20/31] net: cadence_gem: clear RX control descriptor, Peter Maydell, 2020/04/30
- [PULL 17/31] qdev-monitor: print the device's clock with info qtree, Peter Maydell, 2020/04/30
- [PULL 22/31] hw/arm/virt: dt: move creation of /secure-chosen to create_fdt(), Peter Maydell, 2020/04/30
- [PULL 21/31] target/arm: Vectorize integer comparison vs zero, Peter Maydell, 2020/04/30
- [PULL 23/31] hw/arm/virt: dt: add kaslr-seed property, Peter Maydell, 2020/04/30
- [PULL 24/31] target/arm: Restrict the Address Translate write operation to TCG accel, Peter Maydell, 2020/04/30
- [PULL 25/31] target/arm: Make cpu_register() available for other files, Peter Maydell, 2020/04/30
- [PULL 26/31] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[], Peter Maydell, 2020/04/30
- [PULL 27/31] target/arm/cpu: Update coding style to make checkpatch.pl happy, Peter Maydell, 2020/04/30