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[PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT
From: |
Peter Maydell |
Subject: |
[PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT |
Date: |
Tue, 16 Feb 2021 16:16:44 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
A proper syndrome is required to fill in the proper si_code.
Use page_get_flags to determine permission vs translation for user-only.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210212184902.1251044-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/cpu_loop.c | 24 +++++++++++++++++++++---
target/arm/tlb_helper.c | 15 +++++++++------
2 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 42b9c15f536..4e43906e66a 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -23,6 +23,7 @@
#include "cpu_loop-common.h"
#include "qemu/guest-random.h"
#include "hw/semihosting/common-semi.h"
+#include "target/arm/syndrome.h"
#define get_user_code_u32(x, gaddr, env) \
({ abi_long __r = get_user_u32((x), (gaddr)); \
@@ -76,7 +77,7 @@
void cpu_loop(CPUARMState *env)
{
CPUState *cs = env_cpu(env);
- int trapnr;
+ int trapnr, ec, fsc;
abi_long ret;
target_siginfo_t info;
@@ -117,9 +118,26 @@ void cpu_loop(CPUARMState *env)
case EXCP_DATA_ABORT:
info.si_signo = TARGET_SIGSEGV;
info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
info._sifields._sigfault._addr = env->exception.vaddress;
+
+ /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
+ ec = syn_get_ec(env->exception.syndrome);
+ assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
+
+ /* Both EC have the same format for FSC, or close enough. */
+ fsc = extract32(env->exception.syndrome, 0, 6);
+ switch (fsc) {
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+ info.si_code = TARGET_SEGV_MAPERR;
+ break;
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+ info.si_code = TARGET_SEGV_ACCERR;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
case EXCP_DEBUG:
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index df85079d9f0..9609333cbdf 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -154,21 +154,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
bool probe, uintptr_t retaddr)
{
ARMCPU *cpu = ARM_CPU(cs);
+ ARMMMUFaultInfo fi = {};
#ifdef CONFIG_USER_ONLY
- cpu->env.exception.vaddress = address;
- if (access_type == MMU_INST_FETCH) {
- cs->exception_index = EXCP_PREFETCH_ABORT;
+ int flags = page_get_flags(useronly_clean_ptr(address));
+ if (flags & PAGE_VALID) {
+ fi.type = ARMFault_Permission;
} else {
- cs->exception_index = EXCP_DATA_ABORT;
+ fi.type = ARMFault_Translation;
}
- cpu_loop_exit_restore(cs, retaddr);
+
+ /* now we have a real cpu fault */
+ cpu_restore_state(cs, retaddr, true);
+ arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
#else
hwaddr phys_addr;
target_ulong page_size;
int prot, ret;
MemTxAttrs attrs = {};
- ARMMMUFaultInfo fi = {};
ARMCacheAttrs cacheattrs = {};
/*
--
2.20.1
- [PULL 15/40] exec: Rename guest_{addr,range}_valid to *_untagged, (continued)
- [PULL 15/40] exec: Rename guest_{addr,range}_valid to *_untagged, Peter Maydell, 2021/02/16
- [PULL 16/40] linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged, Peter Maydell, 2021/02/16
- [PULL 17/40] linux-user: Move lock_user et al out of line, Peter Maydell, 2021/02/16
- [PULL 18/40] linux-user: Fix types in uaccess.c, Peter Maydell, 2021/02/16
- [PULL 19/40] linux-user: Handle tags in lock_user/unlock_user, Peter Maydell, 2021/02/16
- [PULL 20/40] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE, Peter Maydell, 2021/02/16
- [PULL 21/40] target/arm: Improve gen_top_byte_ignore, Peter Maydell, 2021/02/16
- [PULL 22/40] target/arm: Use the proper TBI settings for linux-user, Peter Maydell, 2021/02/16
- [PULL 24/40] linux-user/aarch64: Implement PROT_MTE, Peter Maydell, 2021/02/16
- [PULL 23/40] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG, Peter Maydell, 2021/02/16
- [PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT,
Peter Maydell <=
- [PULL 30/40] target/arm: Enable MTE for user-only, Peter Maydell, 2021/02/16
- [PULL 28/40] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error, Peter Maydell, 2021/02/16
- [PULL 34/40] hw/arm: Add I2C sensors and EEPROM for GSJ machine, Peter Maydell, 2021/02/16
- [PULL 32/40] hw/i2c: Implement NPCM7XX SMBus Module Single Mode, Peter Maydell, 2021/02/16
- [PULL 29/40] target/arm: Add allocation tag storage for user mode, Peter Maydell, 2021/02/16
- [PULL 35/40] hw/i2c: Add a QTest for NPCM7XX SMBus Device, Peter Maydell, 2021/02/16
- [PULL 25/40] target/arm: Split out syndrome.h from internals.h, Peter Maydell, 2021/02/16
- [PULL 31/40] tests/tcg/aarch64: Add mte smoke tests, Peter Maydell, 2021/02/16
- [PULL 27/40] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault, Peter Maydell, 2021/02/16
- [PULL 39/40] hw/arm: Add npcm7xx emc model, Peter Maydell, 2021/02/16