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[PULL 29/40] target/arm: Add allocation tag storage for user mode
From: |
Peter Maydell |
Subject: |
[PULL 29/40] target/arm: Add allocation tag storage for user mode |
Date: |
Tue, 16 Feb 2021 16:16:47 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Use the now-saved PAGE_ANON and PAGE_MTE bits,
and the per-page saved data.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210212184902.1251044-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index d55f8d1e1ed..1c569336eae 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -78,8 +78,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int
ptr_mmu_idx,
int tag_size, uintptr_t ra)
{
#ifdef CONFIG_USER_ONLY
- /* Tag storage not implemented. */
- return NULL;
+ uint64_t clean_ptr = useronly_clean_ptr(ptr);
+ int flags = page_get_flags(clean_ptr);
+ uint8_t *tags;
+ uintptr_t index;
+
+ if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) {
+ /* SIGSEGV */
+ arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
+ ptr_mmu_idx, false, ra);
+ g_assert_not_reached();
+ }
+
+ /* Require both MAP_ANON and PROT_MTE for the page. */
+ if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) {
+ return NULL;
+ }
+
+ tags = page_get_target_data(clean_ptr);
+ if (tags == NULL) {
+ size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1);
+ tags = page_alloc_target_data(clean_ptr, alloc_size);
+ assert(tags != NULL);
+ }
+
+ index = extract32(ptr, LOG2_TAG_GRANULE + 1,
+ TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1);
+ return tags + index;
#else
uintptr_t index;
CPUIOTLBEntry *iotlbentry;
--
2.20.1
- [PULL 20/40] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE, (continued)
- [PULL 20/40] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE, Peter Maydell, 2021/02/16
- [PULL 21/40] target/arm: Improve gen_top_byte_ignore, Peter Maydell, 2021/02/16
- [PULL 22/40] target/arm: Use the proper TBI settings for linux-user, Peter Maydell, 2021/02/16
- [PULL 24/40] linux-user/aarch64: Implement PROT_MTE, Peter Maydell, 2021/02/16
- [PULL 23/40] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG, Peter Maydell, 2021/02/16
- [PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT, Peter Maydell, 2021/02/16
- [PULL 30/40] target/arm: Enable MTE for user-only, Peter Maydell, 2021/02/16
- [PULL 28/40] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error, Peter Maydell, 2021/02/16
- [PULL 34/40] hw/arm: Add I2C sensors and EEPROM for GSJ machine, Peter Maydell, 2021/02/16
- [PULL 32/40] hw/i2c: Implement NPCM7XX SMBus Module Single Mode, Peter Maydell, 2021/02/16
- [PULL 29/40] target/arm: Add allocation tag storage for user mode,
Peter Maydell <=
- [PULL 35/40] hw/i2c: Add a QTest for NPCM7XX SMBus Device, Peter Maydell, 2021/02/16
- [PULL 25/40] target/arm: Split out syndrome.h from internals.h, Peter Maydell, 2021/02/16
- [PULL 31/40] tests/tcg/aarch64: Add mte smoke tests, Peter Maydell, 2021/02/16
- [PULL 27/40] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault, Peter Maydell, 2021/02/16
- [PULL 39/40] hw/arm: Add npcm7xx emc model, Peter Maydell, 2021/02/16
- [PULL 33/40] hw/arm: Add I2C sensors for NPCM750 eval board, Peter Maydell, 2021/02/16
- [PULL 36/40] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode, Peter Maydell, 2021/02/16
- [PULL 37/40] MAINTAINERS: add myself maintainer for the clock framework, Peter Maydell, 2021/02/16
- [PULL 40/40] tests/qtests: Add npcm7xx emc model test, Peter Maydell, 2021/02/16
- [PULL 38/40] hw/net: Add npcm7xx emc model, Peter Maydell, 2021/02/16