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[PULL 30/40] target/arm: Enable MTE for user-only
From: |
Peter Maydell |
Subject: |
[PULL 30/40] target/arm: Enable MTE for user-only |
Date: |
Tue, 16 Feb 2021 16:16:48 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210212184902.1251044-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 70cfcbc9181..b8bc89e71fc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -209,6 +209,21 @@ static void arm_cpu_reset(DeviceState *dev)
* Note that this must match useronly_clean_ptr.
*/
env->cp15.tcr_el[1].raw_tcr = (1ULL << 37);
+
+ /* Enable MTE */
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ /* Enable tag access, but leave TCF0 as No Effect (0). */
+ env->cp15.sctlr_el[1] |= SCTLR_ATA0;
+ /*
+ * Exclude all tags, so that tag 0 is always used.
+ * This corresponds to Linux current->thread.gcr_incl = 0.
+ *
+ * Set RRND, so that helper_irg() will generate a seed later.
+ * Here in cpu_reset(), the crypto subsystem has not yet been
+ * initialized.
+ */
+ env->cp15.gcr_el1 = 0x1ffff;
+ }
#else
/* Reset into the highest available EL */
if (arm_feature(env, ARM_FEATURE_EL3)) {
--
2.20.1
- [PULL 16/40] linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged, (continued)
- [PULL 16/40] linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged, Peter Maydell, 2021/02/16
- [PULL 17/40] linux-user: Move lock_user et al out of line, Peter Maydell, 2021/02/16
- [PULL 18/40] linux-user: Fix types in uaccess.c, Peter Maydell, 2021/02/16
- [PULL 19/40] linux-user: Handle tags in lock_user/unlock_user, Peter Maydell, 2021/02/16
- [PULL 20/40] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE, Peter Maydell, 2021/02/16
- [PULL 21/40] target/arm: Improve gen_top_byte_ignore, Peter Maydell, 2021/02/16
- [PULL 22/40] target/arm: Use the proper TBI settings for linux-user, Peter Maydell, 2021/02/16
- [PULL 24/40] linux-user/aarch64: Implement PROT_MTE, Peter Maydell, 2021/02/16
- [PULL 23/40] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG, Peter Maydell, 2021/02/16
- [PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT, Peter Maydell, 2021/02/16
- [PULL 30/40] target/arm: Enable MTE for user-only,
Peter Maydell <=
- [PULL 28/40] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error, Peter Maydell, 2021/02/16
- [PULL 34/40] hw/arm: Add I2C sensors and EEPROM for GSJ machine, Peter Maydell, 2021/02/16
- [PULL 32/40] hw/i2c: Implement NPCM7XX SMBus Module Single Mode, Peter Maydell, 2021/02/16
- [PULL 29/40] target/arm: Add allocation tag storage for user mode, Peter Maydell, 2021/02/16
- [PULL 35/40] hw/i2c: Add a QTest for NPCM7XX SMBus Device, Peter Maydell, 2021/02/16
- [PULL 25/40] target/arm: Split out syndrome.h from internals.h, Peter Maydell, 2021/02/16
- [PULL 31/40] tests/tcg/aarch64: Add mte smoke tests, Peter Maydell, 2021/02/16
- [PULL 27/40] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault, Peter Maydell, 2021/02/16
- [PULL 39/40] hw/arm: Add npcm7xx emc model, Peter Maydell, 2021/02/16
- [PULL 33/40] hw/arm: Add I2C sensors for NPCM750 eval board, Peter Maydell, 2021/02/16