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[PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetr
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree |
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Date: |
Sat, 23 Oct 2021 23:47:41 +0200 |
Convert instructions with a 5-bit immediate value to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 15 +++++
target/mips/tcg/msa_translate.c | 99 +++++++++------------------------
2 files changed, 40 insertions(+), 74 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 86aa66f05b9..5aaa85456da 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -19,6 +19,8 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst
+@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws=0
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
@@ -30,6 +32,19 @@ BZ 010001 110 .. ..... ................
@bz
BNZ 010001 111 .. ..... ................ @bz
{
+ ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
+ SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
+ MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
+ MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
+ MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
+ MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
+
+ CEQI 011110 000 .. ..... ..... ..... 000111 @s5
+ CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
+ CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
+ CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
+ CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
+
LDI 011110 110 .. .......... ..... 000111 @ldi
MSA 011110 --------------------------
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7c1bbfaec61..962aef601cb 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
OPC_MSA_I8_00 = 0x00 | OPC_MSA,
OPC_MSA_I8_01 = 0x01 | OPC_MSA,
OPC_MSA_I8_02 = 0x02 | OPC_MSA,
- OPC_MSA_I5_06 = 0x06 | OPC_MSA,
- OPC_MSA_I5_07 = 0x07 | OPC_MSA,
OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
OPC_MSA_3R_0D = 0x0D | OPC_MSA,
@@ -58,19 +56,6 @@ enum {
};
enum {
- /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
- OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
- OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
- OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
- OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
- OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
- OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
- OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
-
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
@@ -341,6 +326,9 @@ static inline bool check_msa_access(DisasContext *ctx)
return true;
}
+#define TRANS_MSA(NAME, trans_func, gen_func) \
+ TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
+
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@@ -507,69 +495,36 @@ static void gen_msa_i8(DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
-static void gen_msa_i5(DisasContext *ctx)
+static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
+ TCGv_i32, TCGv_i32))
{
-#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
- uint8_t u5 = extract32(ctx->opcode, 16, 5);
+ TCGv_i32 tdf = tcg_constant_i32(a->df);
+ TCGv_i32 twd = tcg_const_i32(a->wd);
+ TCGv_i32 tws = tcg_const_i32(a->ws);
+ TCGv_i32 timm = tcg_const_i32(a->sa);
- TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
- TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
- TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
- TCGv_i32 timm = tcg_temp_new_i32();
- tcg_gen_movi_i32(timm, u5);
+ gen_msa_i5(cpu_env, tdf, twd, tws, timm);
- switch (MASK_MSA_I5(ctx->opcode)) {
- case OPC_ADDVI_df:
- gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_SUBVI_df:
- gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_U_df:
- gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_U_df:
- gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CEQI_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_U_df:
- gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_U_df:
- gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(tdf);
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(timm);
+
+ return true;
}
+TRANS_MSA(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df);
+TRANS_MSA(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df);
+TRANS_MSA(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df);
+TRANS_MSA(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df);
+TRANS_MSA(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df);
+TRANS_MSA(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df);
+TRANS_MSA(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df);
+TRANS_MSA(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df);
+TRANS_MSA(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df);
+TRANS_MSA(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df);
+TRANS_MSA(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df);
+
static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
{
TCGv_i32 tdf;
@@ -2196,10 +2151,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_I8_02:
gen_msa_i8(ctx);
break;
- case OPC_MSA_I5_06:
- case OPC_MSA_I5_07:
- gen_msa_i5(ctx);
- break;
case OPC_MSA_BIT_09:
case OPC_MSA_BIT_0A:
gen_msa_bit(ctx);
--
2.31.1
- [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, (continued)
- [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 10/33] target/mips: Extract df_extract() helper, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23