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[PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree |
Date: |
Sat, 23 Oct 2021 23:47:43 +0200 |
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 3 +++
target/mips/tcg/msa_translate.c | 47 +++++++++++++++++++++------------
2 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 91d71ff560c..6347468a709 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -22,6 +22,7 @@
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws=0
+@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_ldst
@bit ...... ... df:7 ws:5 wd:5 ...... &msa_ldst sa=0
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
@@ -33,6 +34,8 @@ BZ 010001 110 .. ..... ................
@bz
BNZ 010001 111 .. ..... ................ @bz
{
+ SHF 011110 .. ........ ..... ..... 000010 @i8_df
+
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 10bbe25172a..7cb078bfe92 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -57,13 +57,10 @@ enum {
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
- OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
- OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
- OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
/* VEC/2R/2RF instruction */
@@ -454,20 +451,6 @@ static void gen_msa_i8(DisasContext *ctx)
case OPC_BSELI_B:
gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
break;
- case OPC_SHF_B:
- case OPC_SHF_H:
- case OPC_SHF_W:
- {
- uint8_t df = (ctx->opcode >> 24) & 0x3;
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- } else {
- TCGv_i32 tdf = tcg_const_i32(df);
- gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
- tcg_temp_free_i32(tdf);
- }
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -479,6 +462,36 @@ static void gen_msa_i8(DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
+static bool trans_SHF(DisasContext *ctx, arg_msa_ldst *a)
+{
+ TCGv_i32 tdf;
+ TCGv_i32 twd;
+ TCGv_i32 tws;
+ TCGv_i32 timm;
+
+ if (a->df == DF_DOUBLE) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ if (!check_msa_access(ctx)) {
+ return false;
+ }
+
+ tdf = tcg_constant_i32(a->df);
+ twd = tcg_const_i32(a->wd);
+ tws = tcg_const_i32(a->ws);
+ timm = tcg_const_i32(a->sa);
+
+ gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, timm);
+
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(timm);
+
+ return true;
+}
+
static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
TCGv_i32, TCGv_i32))
--
2.31.1
- [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree, (continued)
- [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 10/33] target/mips: Extract df_extract() helper, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23