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[PULL 03/40] target/riscv: correct "code should not be reached" for x-rv
From: |
Alistair Francis |
Subject: |
[PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128 |
Date: |
Sat, 12 Feb 2022 09:59:54 +1000 |
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 +--
target/riscv/gdbstub.c | 3 +++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1cb0436187..5ada71e5bf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -528,9 +528,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
switch (env->misa_mxl_max) {
#ifdef TARGET_RISCV64
case MXL_RV64:
- cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
- break;
case MXL_RV128:
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
break;
#endif
case MXL_RV32:
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index f531a74c2f..9ed049c29e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -64,6 +64,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray
*mem_buf, int n)
case MXL_RV32:
return gdb_get_reg32(mem_buf, tmp);
case MXL_RV64:
+ case MXL_RV128:
return gdb_get_reg64(mem_buf, tmp);
default:
g_assert_not_reached();
@@ -84,6 +85,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
length = 4;
break;
case MXL_RV64:
+ case MXL_RV128:
if (env->xl < MXL_RV64) {
tmp = (int32_t)ldq_p(mem_buf);
} else {
@@ -420,6 +422,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
1, "riscv-32bit-virtual.xml", 0);
break;
case MXL_RV64:
+ case MXL_RV128:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);
--
2.34.1
- [PULL 00/40] riscv-to-apply queue, Alistair Francis, 2022/02/11
- [PULL 01/40] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/11
- [PULL 02/40] Allow setting up to 8 bytes with the generic loader, Alistair Francis, 2022/02/11
- [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128,
Alistair Francis <=
- [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Alistair Francis, 2022/02/11
- [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Alistair Francis, 2022/02/11
- [PULL 07/40] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/11
- [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/11
- [PULL 08/40] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/11
- [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/11
- [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/11
- [PULL 11/40] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/11
- [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/11
- [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/11