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[PULL 17/26] target/arm: Implement FEAT_LPA
From: |
Peter Maydell |
Subject: |
[PULL 17/26] target/arm: Implement FEAT_LPA |
Date: |
Wed, 2 Mar 2022 20:52:21 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
64k pages. The only thing left at this point is to handle the
extra bits in the TTBR and in the table descriptors.
Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't
mask out the high bits when writing to those registers, so no changes
are required there.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-param.h | 2 +-
target/arm/cpu64.c | 2 +-
target/arm/helper.c | 19 ++++++++++++++++---
4 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index f3eabddfb5a..0053ddce208 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -24,6 +24,7 @@ the following architecture extensions:
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
- FEAT_JSCVT (JavaScript conversion instructions)
- FEAT_LOR (Limited ordering regions)
+- FEAT_LPA (Large Physical Address space)
- FEAT_LRCPC (Load-acquire RCpc instructions)
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
- FEAT_LSE (Large System Extensions)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 5f9c288b1a6..b59d505761c 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -10,7 +10,7 @@
#ifdef TARGET_AARCH64
# define TARGET_LONG_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 48
+# define TARGET_PHYS_ADDR_SPACE_BITS 52
# define TARGET_VIRT_ADDR_SPACE_BITS 52
#else
# define TARGET_LONG_BITS 32
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1de31ffb406..d88662cef68 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -795,7 +795,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_aa64pfr1 = t;
t = cpu->isar.id_aa64mmfr0;
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 28b43472131..950f56599e2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11173,6 +11173,7 @@ static const uint8_t pamax_map[] = {
[3] = 42,
[4] = 44,
[5] = 48,
+ [6] = 52,
};
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
@@ -11564,11 +11565,15 @@ static bool get_phys_addr_lpae(CPUARMState *env,
uint64_t address,
descaddr = extract64(ttbr, 0, 48);
/*
- * If the base address is out of range, raise AddressSizeFault.
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
+ *
+ * Otherwise, if the base address is out of range, raise AddressSizeFault.
* In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
* but we've just cleared the bits above 47, so simplify the test.
*/
- if (descaddr >> outputsize) {
+ if (outputsize > 48) {
+ descaddr |= extract64(ttbr, 2, 4) << 48;
+ } else if (descaddr >> outputsize) {
level = 0;
fault_type = ARMFault_AddressSize;
goto do_fault;
@@ -11620,7 +11625,15 @@ static bool get_phys_addr_lpae(CPUARMState *env,
uint64_t address,
}
descaddr = descriptor & descaddrmask;
- if (descaddr >> outputsize) {
+
+ /*
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
+ * of descriptor. Otherwise, if descaddr is out of range, raise
+ * AddressSizeFault.
+ */
+ if (outputsize > 48) {
+ descaddr |= extract64(descriptor, 12, 4) << 48;
+ } else if (descaddr >> outputsize) {
fault_type = ARMFault_AddressSize;
goto do_fault;
}
--
2.25.1
- [PULL 00/26] target-arm queue, Peter Maydell, 2022/03/02
- [PULL 02/26] hw/arm/mps2-tz.c: Update AN547 documentation URL, Peter Maydell, 2022/03/02
- [PULL 03/26] hw/input/tsc210x: Don't abort on bad SPI word widths, Peter Maydell, 2022/03/02
- [PULL 07/26] tests/qtest: add qtests for npcm7xx sdhci, Peter Maydell, 2022/03/02
- [PULL 08/26] hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>, Peter Maydell, 2022/03/02
- [PULL 09/26] target/arm: Set TCR_EL1.TSZ for user-only, Peter Maydell, 2022/03/02
- [PULL 10/26] target/arm: Fault on invalid TCR_ELx.TxSZ, Peter Maydell, 2022/03/02
- [PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup, Peter Maydell, 2022/03/02
- [PULL 14/26] target/arm: Honor TCR_ELx.{I}PS, Peter Maydell, 2022/03/02
- [PULL 11/26] target/arm: Move arm_pamax out of line, Peter Maydell, 2022/03/02
- [PULL 17/26] target/arm: Implement FEAT_LPA,
Peter Maydell <=
- [PULL 04/26] hw/i2c: flatten pca954x mux device, Peter Maydell, 2022/03/02
- [PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv(), Peter Maydell, 2022/03/02
- [PULL 01/26] mps3-an547: Add missing user ahb interfaces, Peter Maydell, 2022/03/02
- [PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0, Peter Maydell, 2022/03/02
- [PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA, Peter Maydell, 2022/03/02
- [PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1, Peter Maydell, 2022/03/02
- [PULL 22/26] target/arm: Advertise all page sizes for -cpu max, Peter Maydell, 2022/03/02
- [PULL 23/26] target/arm: Implement FEAT_LPA2, Peter Maydell, 2022/03/02
- [PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues, Peter Maydell, 2022/03/02
- [PULL 16/26] target/arm: Implement FEAT_LVA, Peter Maydell, 2022/03/02