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[PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
From: |
Peter Maydell |
Subject: |
[PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA |
Date: |
Wed, 2 Mar 2022 20:52:19 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned address.
This means that we do not have to consider whether or not FEAT_LVA
is enabled, and decide from which bit an address might need to be
extended.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 32 ++++++++++++++++++++++++--------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c002100979f..2eff30d18c6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6423,11 +6423,18 @@ static void dbgwvr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
ARMCPU *cpu = env_archcpu(env);
int i = ri->crm;
- /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
- * register reads and behaves as if values written are sign extended.
+ /*
* Bits [1:0] are RES0.
+ *
+ * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
+ * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
+ * they contain the value written. It is CONSTRAINED UNPREDICTABLE
+ * whether the RESS bits are ignored when comparing an address.
+ *
+ * Therefore we are allowed to compare the entire register, which lets
+ * us avoid considering whether or not FEAT_LVA is actually enabled.
*/
- value = sextract64(value, 0, 49) & ~3ULL;
+ value &= ~3ULL;
raw_write(env, ri, value);
hw_watchpoint_update(cpu, i);
@@ -6473,10 +6480,19 @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
case 0: /* unlinked address match */
case 1: /* linked address match */
{
- /* Bits [63:49] are hardwired to the value of bit [48]; that is,
- * we behave as if the register was sign extended. Bits [1:0] are
- * RES0. The BAS field is used to allow setting breakpoints on 16
- * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
+ /*
+ * Bits [1:0] are RES0.
+ *
+ * It is IMPLEMENTATION DEFINED whether bits [63:49]
+ * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
+ * of the VA field ([48] or [52] for FEAT_LVA), or whether the
+ * value is read as written. It is CONSTRAINED UNPREDICTABLE
+ * whether the RESS bits are ignored when comparing an address.
+ * Therefore we are allowed to compare the entire register, which
+ * lets us avoid considering whether FEAT_LVA is actually enabled.
+ *
+ * The BAS field is used to allow setting breakpoints on 16-bit
+ * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
* a bp will fire if the addresses covered by the bp and the addresses
* covered by the insn overlap but the insn doesn't start at the
* start of the bp address range. We choose to require the insn and
@@ -6489,7 +6505,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
*/
int bas = extract64(bcr, 5, 4);
- addr = sextract64(bvr, 0, 49) & ~3ULL;
+ addr = bvr & ~3ULL;
if (bas == 0) {
return;
}
--
2.25.1
- [PULL 09/26] target/arm: Set TCR_EL1.TSZ for user-only, (continued)
- [PULL 09/26] target/arm: Set TCR_EL1.TSZ for user-only, Peter Maydell, 2022/03/02
- [PULL 10/26] target/arm: Fault on invalid TCR_ELx.TxSZ, Peter Maydell, 2022/03/02
- [PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup, Peter Maydell, 2022/03/02
- [PULL 14/26] target/arm: Honor TCR_ELx.{I}PS, Peter Maydell, 2022/03/02
- [PULL 11/26] target/arm: Move arm_pamax out of line, Peter Maydell, 2022/03/02
- [PULL 17/26] target/arm: Implement FEAT_LPA, Peter Maydell, 2022/03/02
- [PULL 04/26] hw/i2c: flatten pca954x mux device, Peter Maydell, 2022/03/02
- [PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv(), Peter Maydell, 2022/03/02
- [PULL 01/26] mps3-an547: Add missing user ahb interfaces, Peter Maydell, 2022/03/02
- [PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0, Peter Maydell, 2022/03/02
- [PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA,
Peter Maydell <=
- [PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1, Peter Maydell, 2022/03/02
- [PULL 22/26] target/arm: Advertise all page sizes for -cpu max, Peter Maydell, 2022/03/02
- [PULL 23/26] target/arm: Implement FEAT_LPA2, Peter Maydell, 2022/03/02
- [PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues, Peter Maydell, 2022/03/02
- [PULL 16/26] target/arm: Implement FEAT_LVA, Peter Maydell, 2022/03/02
- [PULL 19/26] target/arm: Introduce tlbi_aa64_get_range, Peter Maydell, 2022/03/02
- [PULL 24/26] target/arm: Report KVM's actual PSCI version to guest in dtb, Peter Maydell, 2022/03/02
- [PULL 13/26] target/arm: Use MAKE_64BIT_MASK to compute indexmask, Peter Maydell, 2022/03/02
- [PULL 20/26] target/arm: Fix TLBIRange.base for 16k and 64k pages, Peter Maydell, 2022/03/02
- [PULL 21/26] target/arm: Validate tlbi TG matches translation granule in use, Peter Maydell, 2022/03/02