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[PULL 16/26] target/arm: Implement FEAT_LVA
From: |
Peter Maydell |
Subject: |
[PULL 16/26] target/arm: Implement FEAT_LVA |
Date: |
Wed, 2 Mar 2022 20:52:20 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
This feature is relatively small, as it applies only to
64k pages and thus requires no additional changes to the
table descriptor walking algorithm, only a change to the
minimum TSZ (which is the inverse of the maximum virtual
address space size).
Note that this feature widens VBAR_ELx, but we already
treat the register as being 64 bits wide.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 5 +++++
target/arm/cpu64.c | 1 +
target/arm/helper.c | 9 ++++++++-
5 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 144dc491d95..f3eabddfb5a 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -27,6 +27,7 @@ the following architecture extensions:
- FEAT_LRCPC (Load-acquire RCpc instructions)
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
- FEAT_LSE (Large System Extensions)
+- FEAT_LVA (Large Virtual Address space)
- FEAT_MTE (Memory Tagging Extension)
- FEAT_MTE2 (Memory Tagging Extension)
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 7f38d33b8ea..5f9c288b1a6 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -11,7 +11,7 @@
#ifdef TARGET_AARCH64
# define TARGET_LONG_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 48
-# define TARGET_VIRT_ADDR_SPACE_BITS 48
+# define TARGET_VIRT_ADDR_SPACE_BITS 52
#else
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 40
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c6a4d50e821..c52d56f6699 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4289,6 +4289,11 @@ static inline bool isar_feature_aa64_ccidx(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
}
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
+}
+
static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1171ab16b94..1de31ffb406 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -811,6 +811,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
cpu->isar.id_aa64mmfr2 = t;
t = cpu->isar.id_aa64zfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2eff30d18c6..28b43472131 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11271,7 +11271,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
} else {
max_tsz = 39;
}
- min_tsz = 16; /* TODO: ARMv8.2-LVA */
+
+ min_tsz = 16;
+ if (using64k) {
+ if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
+ min_tsz = 12;
+ }
+ }
+ /* TODO: FEAT_LPA2 */
if (tsz > max_tsz) {
tsz = max_tsz;
--
2.25.1
- [PULL 17/26] target/arm: Implement FEAT_LPA, (continued)
- [PULL 17/26] target/arm: Implement FEAT_LPA, Peter Maydell, 2022/03/02
- [PULL 04/26] hw/i2c: flatten pca954x mux device, Peter Maydell, 2022/03/02
- [PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv(), Peter Maydell, 2022/03/02
- [PULL 01/26] mps3-an547: Add missing user ahb interfaces, Peter Maydell, 2022/03/02
- [PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0, Peter Maydell, 2022/03/02
- [PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA, Peter Maydell, 2022/03/02
- [PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1, Peter Maydell, 2022/03/02
- [PULL 22/26] target/arm: Advertise all page sizes for -cpu max, Peter Maydell, 2022/03/02
- [PULL 23/26] target/arm: Implement FEAT_LPA2, Peter Maydell, 2022/03/02
- [PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues, Peter Maydell, 2022/03/02
- [PULL 16/26] target/arm: Implement FEAT_LVA,
Peter Maydell <=
- [PULL 19/26] target/arm: Introduce tlbi_aa64_get_range, Peter Maydell, 2022/03/02
- [PULL 24/26] target/arm: Report KVM's actual PSCI version to guest in dtb, Peter Maydell, 2022/03/02
- [PULL 13/26] target/arm: Use MAKE_64BIT_MASK to compute indexmask, Peter Maydell, 2022/03/02
- [PULL 20/26] target/arm: Fix TLBIRange.base for 16k and 64k pages, Peter Maydell, 2022/03/02
- [PULL 21/26] target/arm: Validate tlbi TG matches translation granule in use, Peter Maydell, 2022/03/02
- [PULL 26/26] ui/cocoa.m: Remove unnecessary NSAutoreleasePools, Peter Maydell, 2022/03/02
- Re: [PULL 00/26] target-arm queue, Peter Maydell, 2022/03/03