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[PULL 22/26] target/arm: Advertise all page sizes for -cpu max
From: |
Peter Maydell |
Subject: |
[PULL 22/26] target/arm: Advertise all page sizes for -cpu max |
Date: |
Wed, 2 Mar 2022 20:52:26 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
We support 16k pages, but do not advertize that in ID_AA64MMFR0.
The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer
to the same support as stage1 lookups. This setting is deprecated, so
indicate support for all stage2 page sizes directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220301215958.157011-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index d88662cef68..2fdc16bf182 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -796,6 +796,10 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64mmfr0;
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;
--
2.25.1
- [PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup, (continued)
- [PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup, Peter Maydell, 2022/03/02
- [PULL 14/26] target/arm: Honor TCR_ELx.{I}PS, Peter Maydell, 2022/03/02
- [PULL 11/26] target/arm: Move arm_pamax out of line, Peter Maydell, 2022/03/02
- [PULL 17/26] target/arm: Implement FEAT_LPA, Peter Maydell, 2022/03/02
- [PULL 04/26] hw/i2c: flatten pca954x mux device, Peter Maydell, 2022/03/02
- [PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv(), Peter Maydell, 2022/03/02
- [PULL 01/26] mps3-an547: Add missing user ahb interfaces, Peter Maydell, 2022/03/02
- [PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0, Peter Maydell, 2022/03/02
- [PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA, Peter Maydell, 2022/03/02
- [PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1, Peter Maydell, 2022/03/02
- [PULL 22/26] target/arm: Advertise all page sizes for -cpu max,
Peter Maydell <=
- [PULL 23/26] target/arm: Implement FEAT_LPA2, Peter Maydell, 2022/03/02
- [PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues, Peter Maydell, 2022/03/02
- [PULL 16/26] target/arm: Implement FEAT_LVA, Peter Maydell, 2022/03/02
- [PULL 19/26] target/arm: Introduce tlbi_aa64_get_range, Peter Maydell, 2022/03/02
- [PULL 24/26] target/arm: Report KVM's actual PSCI version to guest in dtb, Peter Maydell, 2022/03/02
- [PULL 13/26] target/arm: Use MAKE_64BIT_MASK to compute indexmask, Peter Maydell, 2022/03/02
- [PULL 20/26] target/arm: Fix TLBIRange.base for 16k and 64k pages, Peter Maydell, 2022/03/02
- [PULL 21/26] target/arm: Validate tlbi TG matches translation granule in use, Peter Maydell, 2022/03/02
- [PULL 26/26] ui/cocoa.m: Remove unnecessary NSAutoreleasePools, Peter Maydell, 2022/03/02
- Re: [PULL 00/26] target-arm queue, Peter Maydell, 2022/03/03