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[PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow
From: |
Alistair Francis |
Subject: |
[PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow |
Date: |
Thu, 21 Apr 2022 16:36:18 +1000 |
From: Nicolas Pitre <nico@fluxnic.net>
There is an overflow with the current code where a pmpaddr value of
0x1fffffff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
ea=0xffffffff.
Fix that by simplifying the computation. There is in fact no need for
ctz64() nor special case for -1 to achieve proper results.
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <rq81o86n-17ps-92no-p65o-79o88476266@syhkavp.arg>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 81b61bb65c..151da3fa08 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -141,17 +141,9 @@ static void pmp_decode_napot(target_ulong a, target_ulong
*sa, target_ulong *ea)
0111...1111 2^(XLEN+2)-byte NAPOT range
1111...1111 Reserved
*/
- if (a == -1) {
- *sa = 0u;
- *ea = -1;
- return;
- } else {
- target_ulong t1 = ctz64(~a);
- target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
- target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
- *sa = base;
- *ea = base + range;
- }
+ a = (a << 2) | 0x3;
+ *sa = a & (a + 1);
+ *ea = a | (a + 1);
}
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
--
2.35.1
- [PULL 09/31] target/riscv: cpu: Fixup indentation, (continued)
- [PULL 09/31] target/riscv: cpu: Fixup indentation, Alistair Francis, 2022/04/21
- [PULL 10/31] target/riscv: Allow software access to MIP SEIP, Alistair Francis, 2022/04/21
- [PULL 12/31] target/riscv: optimize condition assign for scale < 0, Alistair Francis, 2022/04/21
- [PULL 14/31] target/riscv: misa to ISA string conversion fix, Alistair Francis, 2022/04/21
- [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension, Alistair Francis, 2022/04/21
- [PULL 13/31] target/riscv: optimize helper for vmv<nr>r.v, Alistair Francis, 2022/04/21
- [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree, Alistair Francis, 2022/04/21
- [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, Alistair Francis, 2022/04/21
- [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults, Alistair Francis, 2022/04/21
- [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM, Alistair Francis, 2022/04/21
- [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow,
Alistair Francis <=
- [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled, Alistair Francis, 2022/04/21
- [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable, Alistair Francis, 2022/04/21
- [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices, Alistair Francis, 2022/04/21
- [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps, Alistair Francis, 2022/04/21
- [PULL 26/31] target/riscv: cpu: Add a config option for native debug, Alistair Francis, 2022/04/21
- [PULL 27/31] target/riscv: csr: Hook debug CSR read/write, Alistair Francis, 2022/04/21
- [PULL 28/31] target/riscv: machine: Add debug state description, Alistair Francis, 2022/04/21
- [PULL 29/31] target/riscv: cpu: Enable native debug feature, Alistair Francis, 2022/04/21