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[PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RIS
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From: |
Alistair Francis |
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Subject: |
[PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT |
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Date: |
Thu, 21 Apr 2022 16:36:20 +1000 |
From: Frank Chang <frank.chang@sifive.com>
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesses.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Message-Id: <20220420080901.14655-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aclint.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index e43b050e92..37e9ace801 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -208,6 +208,10 @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = {
.valid = {
.min_access_size = 4,
.max_access_size = 8
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
}
};
--
2.35.1
- [PULL 10/31] target/riscv: Allow software access to MIP SEIP, (continued)
- [PULL 10/31] target/riscv: Allow software access to MIP SEIP, Alistair Francis, 2022/04/21
- [PULL 12/31] target/riscv: optimize condition assign for scale < 0, Alistair Francis, 2022/04/21
- [PULL 14/31] target/riscv: misa to ISA string conversion fix, Alistair Francis, 2022/04/21
- [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension, Alistair Francis, 2022/04/21
- [PULL 13/31] target/riscv: optimize helper for vmv<nr>r.v, Alistair Francis, 2022/04/21
- [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree, Alistair Francis, 2022/04/21
- [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, Alistair Francis, 2022/04/21
- [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults, Alistair Francis, 2022/04/21
- [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM, Alistair Francis, 2022/04/21
- [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow, Alistair Francis, 2022/04/21
- [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT,
Alistair Francis <=
- [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled, Alistair Francis, 2022/04/21
- [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable, Alistair Francis, 2022/04/21
- [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices, Alistair Francis, 2022/04/21
- [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps, Alistair Francis, 2022/04/21
- [PULL 26/31] target/riscv: cpu: Add a config option for native debug, Alistair Francis, 2022/04/21
- [PULL 27/31] target/riscv: csr: Hook debug CSR read/write, Alistair Francis, 2022/04/21
- [PULL 28/31] target/riscv: machine: Add debug state description, Alistair Francis, 2022/04/21
- [PULL 29/31] target/riscv: cpu: Enable native debug feature, Alistair Francis, 2022/04/21
- [PULL 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Alistair Francis, 2022/04/21